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A1324 PDF预览

A1324

更新时间: 2024-12-01 08:23:15
品牌 Logo 应用领域
急速微 - ALLEGRO 传感器
页数 文件大小 规格书
12页 286K
描述
Low Noise, Linear Hall Effect Sensor ICs with Analog Output

A1324 数据手册

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A1324, A1325, and A1326  
Low Noise, Linear Hall Effect Sensor ICs with Analog Output  
Description  
Features and Benefits  
New applications for linear output Hall-effect devices, such  
as displacement, angular position, and current measurement,  
require high accuracy in conjunction with small package size.  
The Allegro® A1324, A1325, and A1326 linear Hall-effect  
sensorICsaredesignedspecificallytoachievebothgoals.This  
temperature-stable device is available in a miniature surface  
mount package (SOT23W) and an ultra-mini through-hole  
single in-line package.  
• Temperature-stable quiescent output voltage and sensitivity  
• Output voltage proportional to magnetic flux density  
• Low-noise output increases accuracy  
• Precise recoverability after temperature cycling  
• Ratiometric rail-to-rail output  
• Wide ambient temperature range: –40°C to 150°C  
• Immune to mechanical stress  
• Solid-state reliability  
• Enhanced EMC performance for stringent automotive  
applications  
These ratiometric Hall effect sensor ICs provide a voltage  
output that is proportional to the applied magnetic field. They  
featureaquiescentvoltageoutputof50%ofthesupplyvoltage.  
The A1324/25/26 feature factory programmed sensitivities of  
5.0 mV/G, 3.125 mV/G, and 2.5 mV/G, respectively.  
Packages  
3-pin ultramini SIP  
1.5 mm × 4 mm × 3 mm  
(suffix UA)  
3-pin SOT23-W  
2 mm × 3 mm × 1 mm  
(suffix LH)  
The features of these linear devices make them ideal for use in  
automotiveandindustrialapplicationsrequiringhighaccuracy,  
and are guaranteed through an extended temperature range,  
–40°C to 150°C.  
Each BiCMOS monolithic circuit integrates a Hall element,  
temperature-compensating circuitry to reduce the intrinsic  
sensitivity drift of the Hall element, a small-signal high-gain  
amplifier, a clamped low-impedance output stage, and a  
proprietary dynamic offset cancellation technique.  
These devices are available in a 3-pin ultra-mini SIP package  
(UA),anda3-pinsurfacemountSOT-23stylepackage(LH).Both  
are lead (Pb) free, with 100% matte tin leadframe plating.  
Approximate footprint  
Functional Block Diagram  
V+  
To All Subcircuits  
VCC  
VOUT  
Sensitivity and  
Sensitivity TC  
Offset  
Trim Control  
GND  
A1324-DS, Rev. 1  

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