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A-S7C33512NTD36A-166BI PDF预览

A-S7C33512NTD36A-166BI

更新时间: 2024-11-25 03:16:23
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
22页 446K
描述
512KX36 ZBT SRAM, 8.5ns, PBGA165, BGA-165

A-S7C33512NTD36A-166BI 数据手册

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April 2004  
AS7C33512NTD32A  
AS7C33512NTD36A  
®
3.3V 512K × 32/36 SRAM with NTDTM  
Features  
• Asynchronous output enable control  
• Available in 100-pin TQFP and 165-ball BGA package  
• Byte write enables  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
• Self-timed write cycles  
• Organization: 524,288 words × 32 or 36 bits  
™1  
• NTD architecture for efficient bus operation  
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS  
• Fast clock to data access: 3.4/3.8 ns  
• Fast OE access time: 3.4/3.8 ns  
• Fully synchronous operation  
• Flow-through or pipelined mode  
DDQ  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
1. NTDTM is a trademark of Alliance Semiconductor Corporation. All trade-  
marks mentioned in this document are the property of their respective owners.  
Logic block diagram  
19  
19  
A[18:0]  
Q
D
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
19  
R/W  
BWa  
Control  
logic  
CLK  
BWb  
BWc  
BWd  
ADV / LD  
FT  
512K x 32/36  
SRAM  
LBO  
ZZ  
CLK  
Array  
32/36  
32/36  
DQ[a,b,c,d]  
Data  
Input  
Register  
D
Q
32/36  
32/36  
CLK  
32/36  
CLK  
CEN  
CLK  
Output  
Register  
OE  
32/36  
OE  
DQ[a,b,c,d]  
Selection guide  
-166  
6
-133  
7.5  
133  
3.8  
275  
80  
Units  
ns  
Minimum cycle time  
Maximum pipelined clock frequency  
Maximum pipelined clock access time  
Maximum operating current  
166  
3.4  
300  
90  
MHz  
ns  
mA  
mA  
mA  
Maximum standby current  
Maximum CMOS standby current (DC)  
40  
40  
4/30/04, v 2.5  
Alliance Semiconductor  
P. 1 of 22  
Copyright © Alliance Semiconductor. All rights reserved.  

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