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ZL50053QCC PDF预览

ZL50053QCC

更新时间: 2024-02-10 22:55:21
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关电信集成电路
页数 文件大小 规格书
67页 558K
描述
8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs

ZL50053QCC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP, QFP256,1.2SQ,16针数:256
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.61JESD-30 代码:S-PQFP-G256
JESD-609代码:e0长度:28 mm
功能数量:1端子数量:256
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP256,1.2SQ,16封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):225
电源:1.8,3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Other Telecom ICs
标称供电电压:1.8 V表面贴装:YES
电信集成电路类型:DIGITAL TIME SWITCH温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:28 mm
Base Number Matches:1

ZL50053QCC 数据手册

 浏览型号ZL50053QCC的Datasheet PDF文件第2页浏览型号ZL50053QCC的Datasheet PDF文件第3页浏览型号ZL50053QCC的Datasheet PDF文件第4页浏览型号ZL50053QCC的Datasheet PDF文件第5页浏览型号ZL50053QCC的Datasheet PDF文件第6页浏览型号ZL50053QCC的Datasheet PDF文件第7页 
ZL50051/3  
8 K Channel Digital Switch with High Jitter  
Tolerance, Single Rate (8 or 16 Mbps),  
and 64 Inputs and 64 Outputs  
Data Sheet  
December 2003  
Features  
Ordering Information  
8,192 channel x 8,192 channel non-blocking  
unidirectional switching. The Backplane and  
Local inputs and outputs can be combined to form  
a non-blocking switching matrix with 64 input  
streams and 64 output streams  
ZL50051GAC 256 ball PBGA  
ZL50053QCC 256 pin LQFP  
4,096 channel x 4,096 channel non-blocking  
Backplane input to Local output stream switch  
-40°C to +85°C  
4,096 channel x 4,096 channel non-blocking  
Local input to Backplane output stream switch  
Per-stream bit delay for Local and Backplane  
input streams  
4,096 channel x 4,096 channel non-blocking  
Backplane input to Backplane output switch  
Per-stream advancement for Local and Backplane  
output streams  
4,096 channel x 4,096 channel non-blocking  
Local input to Local output stream switch  
Constant 2-frame throughput delay for frame  
integrity  
Backplane port accepts 32 input and 32 output  
ST-BUS streams with a fixed data rate of  
8.192 Mbps, or 16 input and 16 output ST-BUS  
streams with a fixed data rate of 16.384 Mbps  
Per-channel high impedance output control for  
Local and Backplane streams  
Per-channel driven-high output control for Local  
and Backplane streams  
Local port accepts 32 input and 32 output ST-  
BUS streams with a fixed data rate of  
8.192 Mbps, or 16 input and 16 output ST-BUS  
Per-channel message mode for Local and  
Backplane output streams  
streams with a fixed data rate of 16.384 Mbps  
Connection memory block programming for fast  
device initialization  
Exceptional input clock jitter tolerance (17 ns)  
V
V
V
SS (GND)  
DD_IO  
DD_CORE  
RESET  
ODE  
Backplane Data Memories  
(4,096 channels)  
BSTi0-31  
BSTo0-31  
LSTi0-31  
Backplane  
Local  
Backplane  
Interface  
Local  
Interface  
Connection Memory  
(4,096 locations)  
Connection Memory  
(4,096 locations)  
LSTo0-31  
LORS  
Local Data Memories  
BORS  
FP8i  
(4,096 channels)  
FP8o  
FP16o  
C8o  
Input  
Timing Unit  
Output  
Timing  
Unit  
C16o  
Microprocessor Interface  
and Internal Registers  
C8i  
PLL  
Test Port  
V
TMS TDi TDo TCK TRST  
D15-0  
A14-0  
DD_PLL  
DS CS R/W  
DTA  
Figure 1 - ZL50051/3 Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.  

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