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SL1451

更新时间: 2024-02-20 19:12:53
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电视光电二极管
页数 文件大小 规格书
5页 71K
描述
WIDEBAND PLL FM DETECTOR FOR SATELLITE TV

SL1451 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP,Reach Compliance Code:unknown
风险等级:5.78Is Samacsys:N
商用集成电路类型:VIDEO DISCRIMINATOR解调类型:FM
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
功能数量:1端子数量:16
最高工作温度:80 °C最低工作温度:-10 °C
标称输出电压(调频):1500 mV封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
座面最大高度:5.08 mm最大压摆率:70 mA
最大供电电压 (Vsup):9 V最小供电电压 (Vsup):7.4 V
表面贴装:NO温度等级:COMMERCIAL EXTENDED
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

SL1451 数据手册

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ADVANCE INFORMATION  
2042-2·1  
SL1451  
WIDEBAND PLL FM DETECTOR FOR SATELLITE TV  
The SL1451 is a phase locked loop demodulator for use in  
wideband FM systems. It is intended for use with an IF input  
frequency from 300MHz to 700MHz in satellite receivers. It  
consistsofaninputRFamplifier, signalleveldetector, UHFphase  
detector UHF oscillator and video/loop amplifier. Both positive  
and negative going video outputs are available.  
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
LOOP FEEDBACK 1  
0V  
LOOP FEEDBACK 2  
VIDEO OUTPUT  
VIDEO OUTPUT  
OSCILLATOR EMITTER  
OSCILLATOR BASE  
FEATURES  
V
CC  
SL1451  
I Complete PLL System for Wideband FM Demodulator  
I Noise Threshold Performance: 8dB (Typ.)  
OSCILLATOR V  
CC  
RF IN  
PHASE DETECTOR IN  
PHASE DETECTOR IN  
0V  
RF IN  
I
Low External Component Count  
RF AMP GAIN CONTROL  
I Positive and Negative going Video Output  
AGC OUTPUT  
I Demodulates FM Signals with up to 28MHz p-p  
DP16  
Deviation  
Fig. 1 Pin connections - top view  
APPLICATIONS  
I DBS Receivers  
ABSOLUTE MAXIMUM RATINGS  
I Wideband Data Communications Demodulation  
210°C to180°C  
Operating temperature range  
Supply voltage, VCC  
Storage temperature  
Junction temperature  
11V  
255°C to 1150°C  
1175°C  
ORDERING INFORMATION  
SL1451 NA DP (16-lead plastic DIL package)  
PHASE DETECTOR INPUTS  
INPUT INPUT  
RF GAIN  
AGC  
LOOP FEEDBACK  
INPUT 1  
CONTROL  
OUTPUT  
V
CC  
13  
10  
9
6
7
1
680  
570  
12  
11  
14  
15  
RF INPUT  
RF INPUT  
VIDEO OUTPUT  
VIDEO OUTPUT  
PHASE  
DETECTOR  
570  
RF AMPLIFIER  
VIDEO AMPLIFIER  
680  
5
OSC V  
C
3·3k  
2·2k  
16  
2
8
LOOP FEEDBACK  
INPUT 2  
V
1
EE  
V
2
EE  
4
3
OSCILLATOR  
TRANSISTOR  
OSC BASE  
OSC EMITTER  
4·9k  
820  
V 2  
EE  
Fig. 2 Block diagram  

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