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MT8963 PDF预览

MT8963

更新时间: 2024-02-05 10:11:48
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 解码器编解码器PC
页数 文件大小 规格书
32页 609K
描述
Integrated PCM Filter Codec

MT8963 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:QCCN, LCC24,.4SQReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N压伸定律:A-LAW
滤波器:YES最大增益公差:0.25 dB
JESD-30 代码:S-PQCC-N24JESD-609代码:e0
线性编码:NOT AVAILABLE负电源额定电压:-5 V
功能数量:1端子数量:24
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCN
封装等效代码:LCC24,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:+-5 V
认证状态:Not Qualified子类别:Codecs
最大压摆率:0.008 mA标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:PCM CODEC温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
Base Number Matches:1

MT8963 数据手册

 浏览型号MT8963的Datasheet PDF文件第2页浏览型号MT8963的Datasheet PDF文件第3页浏览型号MT8963的Datasheet PDF文件第4页浏览型号MT8963的Datasheet PDF文件第5页浏览型号MT8963的Datasheet PDF文件第6页浏览型号MT8963的Datasheet PDF文件第7页 
ISO2-CMOS MT8960/61/62/63/64/65/66/67  
Integrated PCM Filter Codec  
Data Sheet  
February 2005  
Features  
ST-BUScompatible  
Ordering Information  
MT8960/61/64/65AE  
MT8962/63AE  
MT8962/63/66/67AS  
MT8963ASR  
18 Pin PDIP  
20 Pin PDIP  
20 Pin SOIC  
20 Pin SOIC  
18 Pin PDIP*  
20 Pin PDIP*  
20 Pin SOIC*  
20 Pin SOIC*  
Tubes  
Transmit/Receive filters & PCM Codec in one I.C  
Meets AT&T D3/D4 and CCITT G711 and G712  
µ-Law: MT8960/62/64/67  
Tubes  
Tubes  
Tape & Reel  
Tubes  
MT8960AE1  
MT8962/63AE1  
MT8962AS1  
Tubes  
Tubes  
A-Law: MT8961/63/65/67  
MT8963AS1  
Tubes  
Low power consumption:  
*Pb Free Matte Tin  
-40°C to +85°C  
Op.: 30 mW typ.  
Stby.: 2.5 mW typ.  
Digital Coding Options:  
Description  
MT8964/65/66/67 CCITT Code  
Manufactured in ISO2-CMOS, these integrated  
filter/codecs are designed to meet the demanding  
performance needs of the digital telecommunications  
industry, e.g., PABX, Central Office, Digital telephones.  
MT8960/61/62/63 Alternative Code  
Digitally controlled gain adjust of both filters  
Analog and digital loopback  
Filters and codec independently user accessible  
for testing  
Powerdown mode available  
2.048 MHz master clock input  
Up to six uncommitted control outputs  
±5 V ±5% power supply  
ANUL  
Analog to  
Transmit  
Output  
V
X
Digital PCM  
Encoder  
DSTo  
Register  
Filter  
SD0  
SD1  
SD2  
SD3  
SD4  
SD5  
CSTi  
CA  
F1i  
C2i  
A Register  
8-Bits  
Output  
Control  
Logic  
Register  
B-Register  
8-Bits  
PCM Digital  
to Analog  
Decoder  
Input  
Receive  
Filter  
DSTi  
V
R
Register  
V
GNDA GNDD  
V
V
EE  
Ref  
DD  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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