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5962-9957201QZX PDF预览

5962-9957201QZX

更新时间: 2024-02-01 06:03:44
品牌 Logo 应用领域
赛灵思 - XILINX 现场可编程门阵列可编程逻辑
页数 文件大小 规格书
31页 249K
描述
Field Programmable Gate Array, 1536 CLBs, 322970 Gates, CMOS, CQFP228, CERAMIC, QFP-228

5962-9957201QZX 技术参数

生命周期:Active零件包装代码:QFP
包装说明:CERAMIC, QFP-228针数:228
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5
CLB-Max的组合延迟:0.8 nsJESD-30 代码:S-CQFP-F228
长度:39.37 mm可配置逻辑块数量:1536
等效关口数量:322970端子数量:228
最高工作温度:125 °C最低工作温度:-55 °C
组织:1536 CLBS, 322970 GATES封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:GQFF封装形状:SQUARE
封装形式:FLATPACK, GUARD RING可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Qualified筛选级别:MIL-PRF-38535 Class Q
座面最大高度:3.302 mm最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:0.635 mm端子位置:QUAD
宽度:39.37 mmBase Number Matches:1

5962-9957201QZX 数据手册

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QPro Virtex 2.5V QML  
High-Reliability FPGAs  
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DS002 (v1.5) December 5, 2001  
Preliminary Product Specification  
0.22 µm 5-layer metal process  
100% factory tested  
Features  
Certified to MIL-PRF-38535 (Qualified Manufacturer  
Listing)  
Available to Standard Microcircuit Drawings  
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5962-99572 for XQV300  
5962-99573 for XQV600  
5962-99574 for XQV1000  
Guaranteed over the full military temperature range  
(–55°C to +125°C)  
Ceramic and Plastic Packages  
Fast, high-density Field-Programmable Gate Arrays  
Contact Defense Supply Center Columbus (DSCC)  
for more information at http://www.dscc.dla.mil  
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Densities from 100K to 1M system gates  
System performance up to 200 MHz  
Hot-swappable for Compact PCI  
Description  
The QPro™ Virtex™ FPGA family delivers high-perfor-  
mance, high-capacity programmable logic solutions. Dra-  
matic increases in silicon efficiency result from optimizing  
the new architecture for place-and-route efficiency and  
exploiting an aggressive 5-layer-metal 0.22 µm CMOS pro-  
cess. These advances make QPro Virtex FPGAs powerful  
and flexible alternatives to mask-programmed gate arrays.  
The Virtex family comprises the four members shown in  
Table 1.  
Multi-standard SelectI/O™ interfaces  
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16 high-performance interface standards  
Connects directly to ZBTRAM devices  
Built-in clock-management circuitry  
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Four dedicated delay-locked loops (DLLs) for  
advanced clock control  
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Four primary low-skew global clock distribution  
nets, plus 24 secondary global nets  
Building on experience gained from previous generations of  
FPGAs, the Virtex family represents a revolutionary step  
forward in programmable logic design. Combining a wide  
variety of programmable system features, a rich hierarchy of  
fast, flexible interconnect resources, and advanced process  
technology, the QPro Virtex family delivers a high-speed  
and high-capacity programmable logic solution that  
enhances design flexibility while reducing time-to-market.  
Hierarchical memory system  
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LUTs configurable as 16-bit RAM, 32-bit RAM,  
16-bit dual-ported RAM, or 16-bit Shift Register  
Configurable synchronous dual-ported 4K-bit  
RAMs  
Fast interfaces to external high-performance RAMs  
Flexible architecture that balances speed and density  
Refer to the Virtex™ 2.5V Field Programmable Gate  
Arrayscommercial data sheet for more information on  
device architecture and timing specifications.  
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Dedicated carry logic for high-speed arithmetic  
Dedicated multiplier support  
Cascade chain for wide-input functions  
Abundant registers/latches with clock enable, and  
dual synchronous/asynchronous set and reset  
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Internal 3-state bussing  
IEEE 1149.1 boundary-scan logic  
Die-temperature sensing device  
Supported by FPGA Foundation™ and Alliance  
Development Systems  
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Complete support for Unified Libraries, Relationally  
Placed Macros, and Design Manager  
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Wide selection of PC and workstation platforms  
SRAM-based in-system configuration  
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Unlimited reprogrammability  
Four programming modes  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS002 (v1.5) December 5, 2001  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  

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