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5962-9068901MEA

更新时间： 2024-02-19 08:55:32
品牌 Logo 应用领域
威世 - VISHAY 驱动器复用器开关复用器或开关信号电路光电二极管
页数 文件大小 规格书
9页 128K
描述
High-Speed Drivers with Dual SPDT JFET Switches

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5962-9068901MEA 技术参数

生命周期：TransferredReach Compliance Code：unknown
风险等级：5.55模拟集成电路 - 其他类型：SPDT
JESD-30 代码：R-CDIP-T16标称负供电电压 (Vsup)：-15 V
信道数量：1功能数量：2
端子数量：16标称断态隔离度：55 dB
最大通态电阻 (Ron)：10 Ω最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified筛选级别：MIL-STD-883
标称供电电压 (Vsup)：15 V表面贴装：NO
最长断开时间：200 ns最长接通时间：400 ns
技术：JFET温度等级：MILITARY
端子形式：THROUGH-HOLE端子位置：DUAL
Base Number Matches：1

5962-9068901MEA 数据手册

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DG189/190/191  
Vishay Siliconix  
High-Speed Drivers with Dual SPDT JFET Switches  
FEATURES  
BENEFITS  
APPLICATIONS  
D Constant On-Resistance Over  
D Low Distortion  
D Audio Switching  
D Video Switching  
D Sample/Hold  
Entire Analog Range  
D Eliminates Large Signal Errors  
D High Precision  
D Low Leakage  
D Low Crosstalk  
D Rad Hardness  
D High Bandwidth Capability  
D Fault Protection  
D Guidance and Control Systems  
D Aerospace  
DESCRIPTION  
The DG189/190/191 are precision dual single-pole,  
double-throw (SPDT) analog switches designed to provide  
accurate switching of video and audio signals. This series is  
To achieve fast and accurate switch performance, each device  
comprises four n-channel JFET transistors and a TTL  
compatible bipolar driver. The driver is designed to achieve  
break-before-make switching action, eliminating the  
inadvertent shorting between channels and the crosstalk  
which would result. In the on state, each switch conducts  
current equally well in either direction. In the off condition, the  
switches will block up to 20 V peak-to-peak, with feedthrough  
of less than −60 dB at 10 MHz.  
ideally suited for applications requiring  
on-resistance over the entire analog range.  
a
constant  
The major difference in the devices is the on-resistance  
(DG189—10 ꢀ , DG190—30 ꢀ , DG191—75 ꢂ Reduced  
ꢀ
ꢁ
errors are achieved through low leakage current (ID(on)  
< 2 nA). Applications which benefit from the flat JFET  
on-resistance include audio switching, video switching, and  
data acquisition.  
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION  
Dual-In-Line  
Flat Package  
D
S
1
1
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
14  
13  
12  
11  
10  
9
S
D
S
3
4
4
2
2
2
NC  
IN  
1
2
3
4
5
6
7
D
D
S
3
1
D
3
V−  
D
S
S
3
V
R
1
IN  
IN  
1
S
D
V
L
4
V+  
V−*  
V+  
IN  
4
8
V
L
V
R
NC  
2
Top View  
D
2
S
2
Refer to JAN38510 Information, Military Section  
*Common to Substrate and Case  
Top View  
TRUTH TABLE  
Logic  
SW1, SW2  
SW3, SW4  
0
1
OFF  
ON  
ON  
OFF  
Logic “0” v 0.8 V  
Logic “1” w 2.4 V  
Document Number: 70034  
S-51140—Rev. D, 20-Jun-05  
www.vishay.com  
1
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