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V03602-01XE PDF预览

V03602-01XE

更新时间: 2022-09-15 00:37:22
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
7页 111K
描述
16-BIT D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

V03602-01XE 数据手册

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SN74ACT16373Q-EP  
16-BIT D-TYPE TRANSPARENT LATCH  
WITH 3-STATE OUTPUTS  
SCAS678B – MAY 2002 – REVISED JULY 2002  
DL PACKAGE  
(TOP VIEW)  
Controlled Baseline  
– One Assembly/Test Site, One Fabrication  
Site  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
Extended Temperature Performance of  
–40°C to 125°C  
2
3
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
4
5
Enhanced Product Change Notification  
6
V
V
7
Qualification Pedigree  
CC  
CC  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
8
Member of the Texas Instruments  
Widebus Family  
9
10  
11  
12  
13  
14  
Inputs Are TTL-Voltage Compatible  
3-State Bus Driving True Outputs  
Full Parallel Access for Loading  
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
GND 15  
2Q3 16  
2Q4 17  
34 GND  
33 2D3  
32 2D4  
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, highly  
accelerated stress test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life.  
18  
19  
20  
21  
22  
23  
24  
31  
30  
29  
28  
27  
26  
25  
V
V
CC  
CC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
description  
The SN74ACT16373Q-EP is a 16-bit D-type  
transparent latch with 3-state outputs, designed  
specifically for driving highly capacitive or  
relatively low-impedance loads. It is particularly  
suitable for implementing buffer registers, I/O  
ports, bidirectional bus drivers, and working  
registers.  
This device can be used as two 8-bit latches or one 16-bit latch. The Q outputs of the latches follow the data  
(D) inputs if the latch-enable (LE) input is taken high. When LE is taken low, the Q outputs are latched at the  
levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low  
logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
buslinessignificantly. Thehigh-impedancestateandtheincreaseddriveprovidethecapabilitytodrivebuslines  
in a bus-organized system, without need for interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2002, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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