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CY74FCT163H374CPAC PDF预览

CY74FCT163H374CPAC

更新时间： 2024-01-05 06:45:14
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路光电二极管驱动
页数 文件大小 规格书
10页 126K
描述
16-Bit Registers

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CY74FCT163H374CPAC 技术参数

生命周期：Transferred零件包装代码：SSOP
包装说明：SSOP,针数：48
Reach Compliance Code：unknown风险等级：5.5
其他特性：BUS HOLD I/P'S系列：FCT
JESD-30 代码：R-PDSO-G48长度：15.875 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
传播延迟（tpd）：5.2 ns认证状态：Not Qualified
座面最大高度：2.794 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

CY74FCT163H374CPAC 数据手册

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Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT163374  
CY74FCT163H374  
SCCS050 - March 1997 - Revised March 2000  
16-Bit Registers  
Features  
Functional Description  
• Low power, pin-compatible replacement for LCX and  
LPT families  
• 5V tolerant inputs and outputs  
These devices are 16-bit D-type registers designed for use as  
buffered registers in high-speed, low power bus applications.  
These devices can be used as two independent 8-bit registers  
or as a single 16-bit register by connecting the output Enable  
(OE) and Clock (CLK) inputs. The outputs are 24-mA balanced  
output drivers with current limiting resistors to reduce the need  
for external terminating resistors, and provide for minimal  
undershoot and reduced ground bounce. Flow-through pinout  
and small shrink packaging aid in simplifying board layout.  
• 24 mA balanced drive outputs  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for reduced noise  
• FCT-C speed at 5.2 ns  
• Latch-up performance exceeds JEDEC standard no. 17  
• Typical output skew < 250 ps  
The CY74FCT163H374 has “bus hold” on the data inputs,  
which retains the input’s last state whenever the source driving  
the input goes to high impedance. This eliminates the need for  
pull-up/down resistors and prevents floating inputs.  
• Industrial temperature range of –40˚C to +85˚C  
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)  
• Typical V  
olp  
(ground bounce) performance exceeds Mil  
Std 883D  
The CY74FCT163374 is designed with inputs and outputs  
capable of being driven by 5.0V buses, allowing its use in  
mixed voltage systems as a translator. The outputs are also  
designed with a power off disable feature enabling its use in  
applications requiring live insertion.  
• VCC = 2.7V to 3.6V  
• ESD (HBM) > 2000V  
CY74FCT163H374  
• Bus hold on data inputs  
• Eliminates the need for external pull-up or pull-down  
resistors  
• Devices with bus hold are not recommended for trans-  
lating rail-to-rail CMOS signals to 3.3V logic levels  
Logic Block Diagrams CY74FCT163374, CY74FCT163H374  
Pin Configuration  
SSOP/TSSOP  
Top View  
1
2
3
4
48  
47  
46  
OE  
O
CLK  
1
1
1
D
1
1
1
2
O
D
2
1
1
GND  
O
GND  
D
45  
44  
43  
42  
41  
OE  
OE  
2
1
5
1
1
3
4
1
1
3
4
O
D
6
CLK  
CLK  
2
1
V
CC  
V
CC  
7
O
5
O
6
D
D
1
1
1
1
5
6
8
D
C
D
C
D
1
D
1
1
2
9
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
O
1
O
1
1
2
GND  
O
GND  
D
10  
11  
1
1
7
8
1
1
7
8
O
D
12  
13  
O
O
D
D
2
2
1
2
2
1
2
14  
15  
16  
17  
18  
2
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
GND  
GND  
O
3
O
4
D
D
2
2
3
2
2
4
V
CC  
V
CC  
O
5
D
5
19  
20  
21  
22  
23  
24  
30  
29  
28  
27  
26  
25  
2
2
2
2
O
6
D
6
GND  
O
GND  
D
2
2
7
8
2
7
8
O
D
2
2
OE  
CLK  
2
Lite Drive is a trademark of Cypress Semiconductor Corporation.  
Copyright © 2000, Texas Instruments Incorporated  
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