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74ACT11590 PDF预览

74ACT11590

更新时间: 2024-01-01 11:24:53
品牌 Logo 应用领域
德州仪器 - TI 计数器输出元件
页数 文件大小 规格书
15页 411K
描述
8-BIT BINART COUNTER WITH REGISTERED 3-STATE OUTPUTS

74ACT11590 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP20,.3针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.91其他特性:TCO OUTPUT; REGISTERED OUTPUTS; CENTER VCC/GND PINS
计数方向:UP系列:ACT
JESD-30 代码:R-PDIP-T20长度:24.325 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:80000000 Hz
最大I(ol):0.024 A工作模式:ASYNCHRONOUS
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):13.9 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:80 MHz
Base Number Matches:1

74ACT11590 数据手册

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ꢀ ꢁ ꢂꢃ ꢄꢅꢅꢆ ꢇꢈ  
ꢉ ꢊꢋꢌ ꢄꢍ ꢋꢌꢎ ꢂꢏꢐꢍꢃ ꢑ ꢒꢎ ꢄꢓ ꢏ  
ꢔ ꢌꢄ ꢕꢍ ꢏꢓꢖ ꢌꢗ ꢄꢓ ꢏꢓꢘꢍ ꢙ ꢊꢗꢄꢂꢄ ꢓꢍ ꢑ ꢒꢄ ꢚꢒ ꢄꢗ  
SCAS195 − D3989, MARCH 1992 − REVISED APRIL 1993  
DW OR N PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Parallel Registered Outputs  
Internal Counters Have Direct Clear  
Q
Q
Q
A
CCK  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
B
Flow-Through Architecture Optimizes  
C
Q
CCKEN  
CCLR  
PCB Layout  
D
GND  
GND  
GND  
GND  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
V
CC  
V
CC  
EPIC(Enhanced-Performance Implanted  
OE  
CMOS) 1-µm Process  
Q
Q
F
RCK  
RCO  
E
500-mA Typical Latch-Up Immunity at 125°C  
Q
Q
H
Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
G
description  
The 74ACT11590 contains an 8-bit binary counter that feeds an 8-bit storage register. The storage register has  
parallel outputs. Separate clocks are provided for both the binary counter and storage register.  
The binary counter features a direct clear (CCLR) input and a count-enable (CCKEN) input. For cascading, a  
ripple-carry (RCO) output is provided. Expansion is easily accomplished for two stages by connecting RCO of  
the first stage to CCKEN of the second stage. Cascading for larger count chains can be accomplished by  
connecting RCO of each stage to CCK of the following stage.  
Both the register and the counter have individual positive-edge-triggered clocks. If both clocks are connected  
together, the counter state is always one count ahead of the register. Internal circuitry prevents clocking from  
the clock enable.  
The 74ACT11590 is characterized for operation from 40°C to 85°C.  
logic symbol  
14  
13  
EN3  
C2  
OE  
RCK  
12  
CTR8  
18  
19  
4
RCO  
G1  
1+  
CT = 0  
CCKEN  
CCK  
(CT = 255) Z4  
17  
CCLR  
20  
1
Q
2D  
3
A
B
C
Q
Q
2
3
Q
Q
Q
Q
Q
D
E
F
8
9
10  
11  
G
H
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
EPIC is a trademark of Texas Instruments Incorporated.  
ꢚꢏ ꢑ ꢘꢒ ꢃ ꢄꢌ ꢑꢎ ꢘ ꢂꢄꢂ ꢜꢝ ꢞ ꢟꢠ ꢡꢢ ꢣꢜꢟ ꢝ ꢜꢤ ꢥꢦ ꢠ ꢠ ꢧꢝꢣ ꢢꢤ ꢟꢞ ꢨꢦꢩ ꢪꢜꢥ ꢢꢣ ꢜꢟꢝ ꢫꢢ ꢣꢧ ꢬ  
ꢚꢠ ꢟ ꢫꢦꢥ ꢣ ꢤ ꢥ ꢟꢝ ꢞꢟ ꢠ ꢡ ꢣ ꢟ ꢤ ꢨꢧ ꢥ ꢜꢞ ꢜꢥꢢ ꢣꢜ ꢟꢝꢤ ꢨꢧ ꢠ ꢣꢭ ꢧ ꢣꢧ ꢠ ꢡꢤ ꢟꢞ ꢄꢧꢮ ꢢꢤ ꢌꢝꢤ ꢣꢠ ꢦꢡ ꢧꢝꢣ ꢤ  
ꢤ ꢣ ꢢ ꢝꢫ ꢢ ꢠꢫ ꢯ ꢢ ꢠꢠ ꢢ ꢝ ꢣꢰꢬ ꢚꢠ ꢟ ꢫꢦꢥ ꢣꢜꢟꢝ ꢨꢠ ꢟꢥ ꢧꢤ ꢤꢜ ꢝꢱ ꢫꢟꢧ ꢤ ꢝꢟꢣ ꢝꢧ ꢥꢧ ꢤꢤ ꢢꢠ ꢜꢪ ꢰ ꢜꢝꢥ ꢪꢦꢫ ꢧ  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
Copyright 1993, Texas Instruments Incorporated  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  

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