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74ACT11543DWG4 PDF预览

74ACT11543DWG4

更新时间: 2024-01-24 03:09:02
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
11页 366K
描述
ACT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO28, GREEN, PLASTIC, SOIC-28

74ACT11543DWG4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP28,.4
针数:28Reach Compliance Code:compliant
风险等级:5.54其他特性:INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:ACTJESD-30 代码:R-PDSO-G28
长度:17.9 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP28,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:12.1 ns传播延迟(tpd):13.2 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:7.5 mmBase Number Matches:1

74ACT11543DWG4 数据手册

 浏览型号74ACT11543DWG4的Datasheet PDF文件第2页浏览型号74ACT11543DWG4的Datasheet PDF文件第3页浏览型号74ACT11543DWG4的Datasheet PDF文件第4页浏览型号74ACT11543DWG4的Datasheet PDF文件第5页浏览型号74ACT11543DWG4的Datasheet PDF文件第6页浏览型号74ACT11543DWG4的Datasheet PDF文件第7页 
74ACT11543  
OCTAL REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCAS136 – D3608, JULY 1990 – REVISED APRIL 1993  
DW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
3-State True Outputs  
Back-to-Back Registers for Storage  
CEBA  
A1  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
GBA  
LEBA  
B1  
B2  
B3  
Flow-Through Architecture Optimizes  
2
PCB Layout  
3
A2  
A3  
A4  
GND  
GND  
GND  
GND  
A5  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
4
CC  
5
6
EPIC (Enhanced-Performance Implanted  
B4  
7
CMOS) 1- m Process  
V
V
CC  
CC  
8
500-mA Typical Latch-Up Immunity at 125°C  
9
B5  
B6  
B7  
B8  
LEAB  
GAB  
10  
11  
12  
13  
14  
description  
A6  
A7  
A8  
This 8-bit registered transceiver contains two sets  
of D-type latches for temporary storage of data  
flowing in either direction. Separate latch enable  
(LEAB or LEBA) and output enable (GAB or GBA)  
inputs are provided for each register to permit  
independent control in either direction of data flow.  
CEAB  
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data to B. Having CEAB  
low and LEAB low makes the A-to-B latches transparent; a subsequent low-to-high transition of LEAB puts the  
A latches in the storage mode. With CEAB and GAB both low, the 3-state B outputs are active and reflect the  
data present at the output of the A latches. Data flow from B-to-A is similar, but requires the use of CEBA, LEBA,  
and GBA inputs.  
The 74ACT11543 is characterized for operation from – 40°C to 85°C.  
FUNCTION TABLE  
LATCH  
INPUTS  
LEAB  
OUTPUT BUFFERS  
B1 THRU B8  
STATUS  
CEAB  
GAB  
A TO B  
H
X
X
L
X
H
X
Storing  
Storing  
Z
H
L
L
Z
L
Transparent  
Storing  
Current A Data  
Previous A Data  
L
H
A-to-B data flow is shown: B-to-A flow control is the same except uses  
CEBA, LEBA, and GBA.  
Data present before low-to-high transition of LEAB.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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