ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
GF PACKAGE
D
Single-Chip Parallel Multiple
Instruction/Multiple Data (MIMD) Digital
Signal Processor (DSP)
(BOTTOM VIEW)
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31 33 35
D
D
More Than Two Billion RISC-Equivalent
Operations per Second
AR
AN
AL
AJ
AG
AE
AC
AA
W
U
AP
AM
AK
AH
AF
AD
AB
Y
Master Processor (MP)
– 32-Bit Reduced Instruction Set
Computing (RISC) Processor
– IEEE-754 Floating-Point Capability
– 4K-Byte Instruction Cache
– 4K-Byte Data Cache
D
D
Four Parallel Processors (PP)
– 32-Bit Advanced DSPs
– 64-Bit Opcode Provides Many Parallel
Operations per Cycle
– 2K-Byte Instruction Cache and 8K-Byte
Data RAM per PP
V
T
R
P
N
M
L
K
J
H
G
F
E
Transfer Controller (TC)
– 64-Bit Data Transfers
– Up to 400 Megabytes per Second (MBps)
Transfer Rate
D
C
B
A
– 32-Bit Addressing
– Direct DRAM/VRAM Interface With
Dynamic Bus Sizing
HFH PACKAGE
(TOP VIEW)
– Intelligent Queuing and Cycle
Prioritization
320
1
241
240
D
Video Controller (VC)
– Provides Video Timing and Video
Random-Access Memory (VRAM)
Control
– Dual-Frame Timers for Two Simultaneous
Image-Capture and/or Display Systems
D
D
D
D
D
D
Big- or Little-Endian Operation
50K-Byte On-Chip RAM
4G-Byte Address Space
20-ns Cycle Time
161
160
80
81
3.3-V Operation
†
IEEE Standard 1149.1 Test Access Port
(JTAG)
D
Operating Temperature Range
–55°C to 125°C - M-Temperature
–40°C to 85°C - A-Temperature
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
IEEE Standard 1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture
Copyright 2002, Texas Instruments Incorporated
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1
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