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5962-9321701QSA PDF预览

5962-9321701QSA

更新时间: 2024-02-19 08:30:32
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路信息通信管理
页数 文件大小 规格书
16页 538K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR

5962-9321701QSA 技术参数

生命周期:Active零件包装代码:DFP
包装说明:CERPACK-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.32Is Samacsys:N
系列:ABTJESD-30 代码:R-GDFP-F20
逻辑集成电路类型:D FLIP-FLOP位数:8
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装形状:RECTANGULAR
封装形式:FLATPACK传播延迟(tpd):7.5 ns
认证状态:Qualified筛选级别:MIL-PRF-38535 Class Q
座面最大高度:2.286 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:6.731 mm
最小 fmax:150 MHzBase Number Matches:1

5962-9321701QSA 数据手册

 浏览型号5962-9321701QSA的Datasheet PDF文件第2页浏览型号5962-9321701QSA的Datasheet PDF文件第3页浏览型号5962-9321701QSA的Datasheet PDF文件第4页浏览型号5962-9321701QSA的Datasheet PDF文件第5页浏览型号5962-9321701QSA的Datasheet PDF文件第6页浏览型号5962-9321701QSA的Datasheet PDF文件第7页 
SN54ABT273, SN74ABT273  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCBS185B – FEBRUARY 1991 – REVISED JANUARY 1997  
SN54ABT273 . . . J OR W PACKAGE  
SN74ABT273 . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
CLR  
1Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
8Q  
8D  
7D  
7Q  
6Q  
6D  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
1D  
2D  
at V  
= 5 V, T = 25°C  
CC  
A
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
2Q  
3Q  
3D  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Plastic (N) and Ceramic (J) DIPs, and  
Ceramic Flat (W) Package  
4D  
4Q  
13 5D  
12 5Q  
11  
GND  
CLK  
description  
SN54ABT273 . . . FK PACKAGE  
(TOP VIEW)  
The ’ABT273 are 8-bit positive-edge-triggered  
D-type flip-flops with a direct clear (CLR) input.  
They are particularly suitable for implementing  
buffer and storage registers, shift registers, and  
pattern generators.  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
17  
16  
15  
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
Q outputs on the positive-going edge of the clock  
pulse. Clock triggering occurs at a particular  
voltage level and is not directly related to the  
transition time of the positive-going pulse. When  
the clock (CLK) input is at either the high or low  
level, the D input signal has no effect at the output.  
14 6D  
9 10 11 12 13  
The SN54ABT273 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74ABT273 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLK  
D
X
H
L
CLR  
L
X
L
H
L
H
H
H
H or L  
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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