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5962-9098401MEA PDF预览

5962-9098401MEA

更新时间： 2024-02-14 15:59:41
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路
页数 文件大小 规格书
11页 267K
描述
High-Speed CMOS Logic Dual Decade Ripple Counter

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5962-9098401MEA 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.53其他特性：DIVIDE BY 2 AND DIVIDE BY 5 FUNCTIONS
计数方向：UP系列：HCT
JESD-30 代码：R-GDIP-T16负载/预设输入：YES
逻辑集成电路类型：DECADE COUNTER工作模式：ASYNCHRONOUS
位数：3功能数量：4
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE认证状态：Not Qualified
筛选级别：MIL-STD-883座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL触发器类型：NEGATIVE EDGE
宽度：7.62 mmBase Number Matches：1

5962-9098401MEA 数据手册

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CD74HC390,  
CD54HCT390, CD74HCT390  
Data sheet acquired from Harris Semiconductor  
SCHS185C  
High-Speed CMOS Logic  
September 1997 - Revised October 2003  
Dual Decade Ripple Counter  
Features  
Description  
• Two BCD Decade or Bi-Quinary Counters  
The CD74HC390 and ’HCT390 dual 4-bit decade ripple  
counters are high-speed silicon-gate CMOS devices and are  
pin compatible with low-power Schottky TTL (LSTTL). These  
devices are divided into four separately clocked sections.  
The counters have two divide-by-2 sections and two divide-  
by-5 sections. These sections are normally used in a BCD  
decade or bi-quinary configuration, since they share a com-  
mon master reset (nMR). If the two master reset inputs (1MR  
and 2MR) are used to simultaneously clear all 8 bits of the  
counter, a number of counting configurations are possible  
within one package. The separate clock inputs (nCP0 and  
nCP1) of each section allow ripple counter or frequency divi-  
sion applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100.  
Each section is triggered by the High-to-Low transition of the  
input pulses (nCP0 and nCP1).  
• One Package Can Be Configured to Divide-by-2, 4,  
5,10, 20, 25, 50 or 100  
[ /Title  
(CD74  
HC390  
,
CD74  
HCT39  
0)  
/Sub-  
ject  
(High  
Speed  
CMOS  
• Two Master Reset Inputs to Clear Each Decade  
Counter Individually  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
For BCD decade operation, the nQ0 output is connected to  
the nCP1 input of the divide-by-5 section. For bi-quinary  
decade operation, the nO3 output is connected to the nCP0  
• HC Types  
- 2V to 6V Operation  
input and nQ becomes the decade output.  
0
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
The master reset inputs (1MR and 2MR) are active-High  
asynchronous inputs to each decade counter which oper-  
ates on the portion of the counter identified by the “1” and “2”  
prefixes in the pin configuration. A High level on the nMR  
input overrides the clock and sets the four outputs Low.  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
Ordering Information  
l
OL OH  
TEMP. RANGE  
o
PART NUMBER  
CD54HCT390F3A  
CD74HC390E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
Pinout  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
CD54HCT390  
(CERDIP)  
CD74HC390, CD74HCT390  
(PDIP, SOIC)  
CD74HC390M  
TOP VIEW  
CD74HC390MT  
CD74HC390M96  
CD74HCT390E  
CD74HCT390M  
CD74HCT390MT  
CD74HCT390M96  
1CP0  
1MR  
1
2
3
4
5
6
7
8
16 V  
CC  
15 2CP0  
14 2MR  
13 2Q0  
1Q  
0
1CP1  
1Q  
1Q  
1Q  
12 2CP1  
1
2
3
11 2Q  
10 2Q  
1
2
3
9
2Q  
GND  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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