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5962-8685301CA PDF预览

5962-8685301CA

更新时间: 2024-02-19 05:06:19
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
12页 276K
描述
Dual D Flip-Flop with Set and Reset Positive-Edge Trigger

5962-8685301CA 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:unknown风险等级:5.74
JESD-30 代码:R-XDIP-T14逻辑集成电路类型:D FLIP-FLOP
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
子类别:FF/Latches标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
触发器类型:POSITIVE EDGEBase Number Matches:1

5962-8685301CA 数据手册

 浏览型号5962-8685301CA的Datasheet PDF文件第2页浏览型号5962-8685301CA的Datasheet PDF文件第3页浏览型号5962-8685301CA的Datasheet PDF文件第4页浏览型号5962-8685301CA的Datasheet PDF文件第5页浏览型号5962-8685301CA的Datasheet PDF文件第6页浏览型号5962-8685301CA的Datasheet PDF文件第7页 
CD54HC74, CD74HC74,  
CD54HCT74, CD74HCT74  
Data sheet acquired from Harris Semiconductor  
SCHS124D  
Dual D Flip-Flop with Set and Reset  
Positive-Edge Trigger  
January 1998 - Revised September 2003  
Features  
Description  
• Hysteresis on Clock Inputs for Improved Noise The ’HC74 and ’HCT74 utilize silicon gate CMOS technology  
Immunity and Increased Input Rise and Fall Times  
• Asynchronous Set and Reset  
• Complementary Outputs  
to achieve operating speeds equivalent to LSTTL parts.  
They exhibit the low power consumption of standard CMOS  
integrated circuits, together with the ability to drive 10 LSTTL  
loads.  
[ /Title  
(CD54H  
C74,  
CD74H  
C74,  
This flip-flop has independent DATA, SET, RESET and  
CLOCK inputs and Q and Q outputs. The logic level present  
at the data input is transferred to the output during the  
positive-going transition of the clock pulse. SET and RESET  
are independent of the clock and are accomplished by a low  
level at the appropriate input.  
• Buffered Inputs  
• Typical f  
MAX  
= 50MHz at V = 5V, C = 15pF,  
CC L  
o
CD74H  
CT74)  
/Subject  
(Dual D  
Flip-  
T = 25 C  
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pin compatible  
with the standard LS logic family.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Flop  
with Set  
Ordering Information  
TEMP. RANGE  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
o
PART NUMBER  
CD54HC74F3A  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
CD54HCT74F3A  
CD74HC74E  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
IL  
IH  
at V  
= 5V  
CC  
CD74HC74M  
• HCT Types  
CD74HC74MT  
CD74HC74M96  
CD74HCT74E  
CD74HCT74M  
CD74HCT74MT  
CD74HCT74M96  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

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