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5962-1123701VXC PDF预览

5962-1123701VXC

更新时间: 2024-01-29 14:07:12
品牌 Logo 应用领域
德州仪器 - TI 存储内存集成电路静态存储器
页数 文件大小 规格书
25页 361K
描述
16-Mb RADIATION-HARDENED SRAM

5962-1123701VXC 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:unknown风险等级:5.78
内存集成电路类型:STANDARD SRAM认证状态:Qualified
Base Number Matches:1

5962-1123701VXC 数据手册

 浏览型号5962-1123701VXC的Datasheet PDF文件第2页浏览型号5962-1123701VXC的Datasheet PDF文件第3页浏览型号5962-1123701VXC的Datasheet PDF文件第4页浏览型号5962-1123701VXC的Datasheet PDF文件第5页浏览型号5962-1123701VXC的Datasheet PDF文件第6页浏览型号5962-1123701VXC的Datasheet PDF文件第7页 
SMV512K32-SP  
www.ti.com  
SLVSA21H JUNE 2011REVISED JULY 2013  
16-Mb RADIATION-HARDENED SRAM  
Check for Samples: SMV512K32-SP  
1
FEATURES  
(1)  
20-ns Read, 13.8-ns Write Through Maximum  
Access Time  
Radiation Performance  
Uses Both Substrate Engineering and  
Radiation Hardened by Design (HBD)  
(2)  
Functionally Compatible With Commercial  
512K x 32 SRAM Devices  
TID Immunity > 3e5 rad (Si)  
Built-In EDAC (Error Detection and Correction)  
to Mitigate Soft Errors  
SER < 5e-17 Upsets/Bit-Day  
(Core Using EDAC and Scrub)  
(3)  
Built-In Scrub Engine for Autonomous  
Correction  
Latch up immunity > LET = 110 MeV  
(T = 398K)  
CMOS Compatible Input and Output Level,  
Three State Bidirectional Data Bus  
Available in a 76-Lead Ceramic Quad Flatpack  
(1) Radiation tolerance is a typical value based upon initial device  
qualification. Radiation Data and Lot Acceptance Testing is  
available – contact factory for details.  
3.3 ±0.3-V I/O, 1.8 ±0.15-V CORE  
(2) HardSILTM technology and memory design under a license  
agreement with Silicon Space Technology (SST).  
(3) SER calculated using CREME96 for geosynchronous orbit,  
solar minimum.  
xxx  
xxx  
xxx  
DESCRIPTION  
The SMV512K32 is a high performance asynchronous CMOS SRAM organized as 524,288 words by 32 bits. It is  
pin selectable between two modes: master or slave. The master device selection provides user defined  
autonomous EDAC scrubbing options. The slave device selection employs a scrub on demand feature that can  
be initiated by a master device. Three read cycles and four write cycles (described below) are available  
depending on the user needs.  
Table 1. ORDERING INFORMATION(1)  
TC  
–55°C to 125°C  
25°C  
PACKAGE(2)  
ORDERABLE PART NUMBER  
SMV512K32HFG  
TOP-SIDE MARKING  
SMV512K32HFG  
76-pin HFG  
5962-1123701VXC  
5962-1123701VXC  
SMV512K32HFG/EM(3)  
SMV512K32HFGMPR  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
Web site at www.ti.com.  
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(3) These units are intended for engineering evaluation only. They are processed to a non compliant flow (e.g., no burn-in) and only tested  
at +25°C. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted as to  
performance over temperature or operating life.  
xxx  
HardSILTM is a trademark of Silicon Space Technology (SST).  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2011–2013, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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