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54ACT11010 PDF预览

54ACT11010

更新时间: 2024-01-29 12:18:33
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
5页 69K
描述
TRIPLE 3-INPUT POSITIVE-NAND GATES

54ACT11010 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.91
其他特性:CENTER PIN VCC AND GND系列:ACT
JESD-30 代码:R-GDIP-T16长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.024 A功能数量:3
输入次数:3端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:9.3 ns
传播延迟(tpd):8.7 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

54ACT11010 数据手册

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54ACT11010, 74ACT11010  
TRIPLE 3-INPUT POSITIVE-NAND GATES  
SCAS018A – D2957, JULY 1987 – REVISED APRIL 1993  
54ACT11010 . . . J PACKAGE  
74ACT11010 . . . D OR N PACKAGE  
Inputs Are TTL-Voltage Compatible  
Flow-Through Architecture to Optimize  
(TOP VIEW)  
PCB Layout  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1A  
1Y  
2Y  
GND  
GND  
3Y  
1B  
1C  
2A  
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
V
V
CC  
CC  
500-mA Typical Latch-Up Immunity  
at 125°C  
2B  
2C  
3A  
3C  
3B  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
54ACT11010 . . . FK PACKAGE  
(TOP VIEW)  
description  
These devices contain three independent 3-input  
NAND gates. They perform the Boolean functions  
Y = A B C or Y = A + B + C in positive logic.  
3
2
1
20 19  
18  
2C  
3A  
NC  
3B  
3C  
1C  
1B  
NC  
1A  
1Y  
4
5
6
7
8
The 54ACT11010 is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The 74ACT11010 is characterized for  
operation from – 40°C to 85°C.  
17  
16  
15  
14  
9 10 11 12 13  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
H
L
B
H
X
L
C
H
X
X
L
NC – No internal connection  
L
H
H
H
logic diagram (positive logic)  
X
X
1
X
1A  
2
16  
15  
1B  
1Y  
1C  
logic symbol  
14  
11  
10  
2A  
2B  
2C  
1
1A  
16  
1B  
15  
1C  
14  
2A  
11  
3
6
&
2Y  
3Y  
2
3
6
1Y  
2Y  
3Y  
9
8
7
3A  
3B  
3C  
2B  
10  
2C  
9
3A  
8
3B  
7
3C  
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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