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54AC16472 PDF预览

54AC16472

更新时间： 2024-01-07 20:44:59
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
8页 163K
描述
18-BIT REGISTERED TRANS CIEVERS WITH 3-STATE OUTPUTS

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54AC16472 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete包装说明：DFP, FL56,.4,25
Reach Compliance Code：not_compliantECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.92
Is Samacsys：N其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ACJESD-30 代码：R-GDFP-F56
长度：18.288 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.024 A
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装等效代码：FL56,.4,25封装形状：RECTANGULAR
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3/5 VProp。Delay @ Nom-Sup：14.2 ns
传播延迟（tpd）：10.9 ns认证状态：Not Qualified
座面最大高度：3.05 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：FLAT端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：9.652 mm
Base Number Matches：1

54AC16472 数据手册

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SCAS165A − JUNE 1990 − REVISED APRIL 1996  
54AC16472 . . . WD PACKAGE  
74AC16472 . . . DL PACKAGE  
(TOP VIEW)  
D
Members of the Texas Instruments  
Widebus Family  
3-State True Outputs  
D
D
Flow-Through Architecture Optimizes  
PCB Layout  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
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39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OEAB  
1LEAB  
1A1  
1OEBA  
1LEBA  
1B1  
2
D
D
D
D
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
3
CC  
4
GND  
1A2  
GND  
1B2  
5
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
500-mA Typical Latch-Up Immunity at  
6
1A3  
1B3  
7
V
V
CC  
CC  
8
1A4  
1A5  
1A6  
GND  
1A7  
1A8  
1A9  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B4  
1B5  
1B6  
GND  
1B7  
1B8  
1B9  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
125°C  
9
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) Package Using  
25-mil Center-to-Center Pin Spacings and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Package Using 25-mil Center-to-Center Pin  
Spacings  
10  
11  
12  
13  
14  
15  
16  
17  
18  
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description  
The ’AC16472 are 18-bit registered transceivers  
that contain two sets of D-type latches for  
temporary storage of data flowing in either  
direction. They can be used as two 9-bit  
transceivers or one 18-bit transceiver. Separate  
latch-enable (LEAB or LEBA) and output-enable  
(OEAB or OEBA) inputs are provided for each  
register to permit independent control in either  
direction of data flow.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2A9  
2B7  
2B8  
GND  
2B9  
2LEBA  
2OEBA  
2LEAB  
2OEAB  
When OEAB and LEAB are both low, the A-to-B  
latches are transparent; a subsequent low-to-high  
transition of LEAB puts the A latches in the  
storage mode. With OEAB low, the B outputs are active and reflect the data present at the output of the A latches.  
Data flow from B to A is similar, but requires the use of the LEBA and OEBA inputs.  
The 74AC16472 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count  
and functionality of standard small-outline packages in the same printed-circuit-board area.  
The 54AC16472 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
74AC16472 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
12345678

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