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78Q2120C09-64CGT/F PDF预览

78Q2120C09-64CGT/F

更新时间: 2024-01-18 19:44:41
品牌 Logo 应用领域
TERIDIAN 网络接口电信集成电路电信电路编码器局域网(LAN)标准
页数 文件大小 规格书
35页 589K
描述
10/100BASE-TX Transceiver

78Q2120C09-64CGT/F 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:LEAD FREE, LQFP-64Reach Compliance Code:unknown
风险等级:5.74Is Samacsys:N
数据速率:100000 MbpsJESD-30 代码:S-PQFP-G64
长度:10 mm功能数量:1
端子数量:64收发器数量:1
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Network Interfaces最大压摆率:0.11 mA
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:MANCHESTER ENCODER/DECODER
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

78Q2120C09-64CGT/F 数据手册

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78Q2120C  
10/100BASE-TX  
Transceiver  
DATA SHEET  
January 2009  
DESCRIPTION  
FEATURES  
The 78Q2120C is a 10BASE-T/100BASE-TX Fast  
Ethernet transceiver. It includes integrated MII,  
ENDECs, scrambler/descrambler, dual-speed clock  
recovery, and full-featured auto-negotiation function.  
The transmitter includes an on-chip pulse-shaper and  
a low-power line driver. The receiver has an adaptive  
equalizer and a baseline restoration circuit required  
for accurate clock and data recovery. The transceiver  
interfaces to Category-5 unshielded twisted pair (Cat-  
5 UTP) cabling for 100BASE-TX/10BASE-T and  
Category-3 unshielded twisted pair for 10BASE-T.  
Connection to the line media is via 1:1 isolation  
transformers. No external filter is required. Interface  
to the MAC is accomplished through an IEEE-802.3  
compliant Media Independent Interface (MII). The  
product is fabricated in an advanced CMOS process  
for high performance and low power operation.  
10BASE-T/100BASE-TX IEEE-802.3 compliant  
TX and RX functions requiring a dual 1:1  
isolation transformer interface to the line  
Integrated MII, 10BASE-T/100BASE-TX ENDEC,  
100BASE-TX scrambler/descrambler, and full-  
featured auto-negotiation function  
Full duplex operation capable  
PCS Bypass supports 5-bit symbol interface  
Register-programmable transmit amplitude  
Dual speed digital clock recovery  
Automatic polarity correction during auto-  
negotiation and 10BASE-T signal reception  
Power-saving and power-down modes  
including transmitter disable  
LED indicators: LINK, TX, RX, COL, 100, 10,  
FDX  
User programmable Interrupt pin  
64-Pin TQFP (JEDEC LQFP) package  
Single 3.3 V ± 0.3V Supply  
BLOCK DIAGRAM  
4B/5B Encoder,  
Pulse Shaper  
100M  
10M  
NRZ/NRZI  
Scrambler,  
MLT3 Encoder  
and Filter  
Parallel/Serial  
TXOP/N  
RXIP/N  
RX_CLK  
TX_CLK  
RXD[3:0]  
TX CLK GEN  
MII  
Registers  
&
MDI  
Parallel/Serial,  
ManchesterEncoder
Interface  
Logic  
Auto  
Negotiation  
TXD[3:0]  
Carrier Sense,  
Collision Detect  
Manchester Decoder,  
Parallel/Serial  
10M  
100M  
CLK  
Adaptive EQ,  
Recovery  
Baseline Wander Correct,  
MLT3Decode,NRZI/NRZ
Serial/Parallel  
Descrambler,  
5B/4B Decoder  
Clock Reference  
LEDs  
PS  
LEDL  
LEDBTX  
LEDTX LEDCOL  
LEDRX  
VCC GND  
CKIN 25MHz  
LEDBT  
LEDFX  
Page: 1 of 35  
© 2009 Teridian Semiconductor Corporation  
Rev 1.3  

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