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ETC5057N PDF预览

ETC5057N

更新时间: 2024-02-12 10:10:24
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器过滤器编解码器LTE
页数 文件大小 规格书
18页 155K
描述
SERIAL INTERFACE CODEC/FILTER

ETC5057N 数据手册

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ETC5054  
ETC5057  
SERIAL INTERFACE CODEC/FILTER  
COMPLETE CODEC AND FILTERING SYS-  
TEM (DEVICE) INCLUDING:  
– Transmithigh-pass and low-pass filtering.  
– Receivelow-pass filter with sin x/x correction.  
– ActiveRC noise filters  
µ-lawor A-lawcompatibleCOderandDECoder.  
– Internalprecision voltage reference.  
– Serial I/O interface.  
– Internalauto-zero circuitry.  
DIP16 (Plastic)  
A-LAW 16 PINS (ETC5057FN, 20 PINS)  
µ-LAW WITHOUT SIGNALING, 16 PINS  
(ETC5054FN, 20 PINS)  
MEETS OR EXCEEDS ALL D3/D4 AND  
CCITT SPECIFICATIONS  
ORDERING NUMBERS:  
ETC5057N  
ETC5054N  
5V OPERATION  
±
LOW OPERATING POWER - TYPICALLY 60  
mW  
POWER-DOWN STANDBY MODE - TYPI-  
CALLY 3 mW  
AUTOMATIC POWER-DOWN  
TTL OR CMOS COMPATIBLE DIGITAL IN-  
TERFACES  
SO16 (Wide)  
MAXIMIZES LINE INTERFACE CARD CIR-  
CUIT DENSITY  
0 to 70°C OPERATION  
ORDERING NUMBERS:  
ETC5057D  
ETC5054D  
DESCRIPTION  
The ETC5057/ETC5054 family consists of A-law  
and µ–law monolithic PCM CODEC/filters utilizing  
the A/D and D/A conversion architecture shown in  
the block diagram below, and a serial PCM inter-  
face. The devices are fabricated using double-  
poly CMOS process. The encode portion of each  
device consists of an input gain adjust amplifier,  
an active RC pre-filter which eliminates very high  
frequency noise prior to entering a switched-ca-  
pacitor band-pass filter that rejects signals below  
200 Hz and above 3400 Hz. Also included are  
auto-zero circuitry and a companding coder which  
samples the filtered signal and encodes it in the  
PLCC20  
ORDERING NUMBERS:  
ETC5057FN  
ETC5054FN  
companded A-law or –law PCM format. The de-  
µ
code portion of each device consists of an ex-  
panding decoder, which reconstructs the analog  
signal from the companded A-law or µ–law code,  
a low-pass filter which corrects for the sin x/x re-  
sponse of the decoder output and rejects signals  
above 3400 Hz and is followed by a single-ended  
power amplifier capable of driving low impedance  
loads. The devices require 1.536 MHz, 1.544  
MHz, or 2.048 MHz transmit and receive master  
clocks, which may be asynchronous, transmit and  
receive bit clocks which may vary from 64 kHz to  
2.048 MHz, and transmit and receive frame sync  
pulses. The timing of the frame sync pulses and  
PCM data is compatible with both industry stand-  
ard formats.  
March 2000  
1/18  
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  

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