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E-STE100P PDF预览

E-STE100P

更新时间: 2024-01-10 10:15:52
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 以太网局域网(LAN)标准以太网:16GBASE-T
页数 文件大小 规格书
31页 345K
描述
10/100 FAST ETHERNET 3.3V TRANSCEIVER

E-STE100P 技术参数

生命周期:Obsolete包装说明:LFQFP,
Reach Compliance Code:unknown风险等级:5.81
Is Samacsys:NJESD-30 代码:S-PQFP-G64
长度:10 mm功能数量:1
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH座面最大高度:1.6 mm
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:ETHERNET TRANSCEIVER
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

E-STE100P 数据手册

 浏览型号E-STE100P的Datasheet PDF文件第2页浏览型号E-STE100P的Datasheet PDF文件第3页浏览型号E-STE100P的Datasheet PDF文件第4页浏览型号E-STE100P的Datasheet PDF文件第5页浏览型号E-STE100P的Datasheet PDF文件第6页浏览型号E-STE100P的Datasheet PDF文件第7页 
STE100P  
10/100 FAST ETHERNET 3.3V TRANSCEIVER  
1 DESCRIPTION  
Figure 1. Package  
The STE100P, also referred to as STEPHY1, is a  
high performance Fast Ethernet physical layer in-  
terface for 10Base-T and 100Base-TX applica-  
tions.  
It was designed with advanced CMOS technology  
to provide a Media Independent Interface (MII) for  
easy attachment to 10/100 Media Access Control-  
lers (MAC) and a physical media interface for  
100Base-TX of IEEE802.3u and 10Base-T of  
IEEE802.3.  
The STEPHY1 supports both half-duplex and full-  
duplex operation, at 10 and 100 Mbps operation.  
Its operating mode can be set using auto-negotia-  
tion, parallel detection or manual control. It also al-  
lows for the support of auto-negotiation functions  
for speed and duplex detection.  
TQFP64 (10x10x1.40mm)  
Table 1. Order Codes  
Part Number  
Package  
TQFP64  
TQFP64  
STE100P  
E-STE100P (*)  
(*) ECOPACK® (see Section 9)  
Support for IEEE802.3x flow control  
IEEE802.3u Auto-Negotiation support for  
10Base-T and 100Base-TX  
2 FEATURES  
MII interface  
Standard CSMA/CD or full duplex operation  
supported  
Industrial temperature compliant  
2.1 Industry standard  
IEEE802.3u 100Base-TX and IEEE802.3  
10Base-T compliant  
Figure 2. Block Diagram  
LEDS  
LEDS  
TX Channel  
100Mb/s  
Parallel to  
Serial  
Binary To MLT3  
Encoder  
Scrambler  
4B/5B  
TX_CLK  
TXD[3:0]  
TX_ER  
TX_EN  
NRZ To NRZI  
Encoder  
TRANSMITTER  
10/100  
TXP  
TXN  
10Mb/s  
Link Pulse  
Generator  
NRZ To Manchester  
Encoder  
10 TX  
Filter  
MDC  
MDIO  
Auto  
Negotiation  
System  
Clock  
Loopback  
Clock  
Generation  
REGISTERS  
RXD[3:0]  
RX_ER  
RX_DV  
RX Channel  
Adaptive  
Equalization  
Binary To MLT3  
Decoder  
100Mb/s  
Descrambler  
Code Align  
Serial to  
Parallel  
BaseLine  
Wander  
NRZI To NRZ  
Decoder  
4B/5B  
RX_CLK  
Clock Recovery  
RXP  
RECEIVER  
10/100  
RXN  
10 TX Filter  
SMART  
Squelch  
NRZ To Manchester  
Encoder  
Link Pulse  
Detector  
10Mb/s  
HW  
configuration  
pins  
Clock Recovery  
HW Config  
Power Down  
Rev. 19  
1/31  
February 2006  

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