5秒后页面跳转
74LVC161284TTR PDF预览

74LVC161284TTR

更新时间: 2024-01-15 07:11:14
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
11页 220K
描述
LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER

74LVC161284TTR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-48针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:16 weeks
风险等级:7.6Is Samacsys:N
差分输出:NO驱动器位数:8
输入特性:SCHMITT TRIGGER接口集成电路类型:LINE TRANSCEIVER
接口标准:IEEE 1284JESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:12.5 mm
湿度敏感等级:3功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified最大接收延迟:9 ns
接收器位数:8座面最大高度:1.2 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V电源电压1-最大:5.5 V
电源电压1-分钟:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30最大传输延迟:9 ns
宽度:6.1 mmBase Number Matches:1

74LVC161284TTR 数据手册

 浏览型号74LVC161284TTR的Datasheet PDF文件第2页浏览型号74LVC161284TTR的Datasheet PDF文件第3页浏览型号74LVC161284TTR的Datasheet PDF文件第4页浏览型号74LVC161284TTR的Datasheet PDF文件第5页浏览型号74LVC161284TTR的Datasheet PDF文件第6页浏览型号74LVC161284TTR的Datasheet PDF文件第7页 
74LVC161284  
LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER  
HIGH SPEED: t = 9ns (MAX.) at V = 3V  
PD CC  
LOW POWER DISSIPATION:  
I
=20µA (MAX) at V =3.6V T =85°C  
CC  
CC A  
TTL COMPATIBLE INPUTS  
V =2V (MIN) V =0.8(MAX)  
IH  
IL  
TSSOP  
TUBE  
OPERATING VOLTAGE RANGE:  
(OPR) = 3.0V to 3.6V  
V
CC  
A PORT HAVE STANDARD 4mA TOTEM  
POLE OUTPUT  
ORDER CODES  
PACKAGE  
T & R  
B PORT HIGH DRIVE SOURCE/SINK  
CAPABILITY OF 14mA  
TSSOP  
74LVC161284TTR  
SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE)  
AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR  
BIDIRECTIONAL PARALLEL  
PIN CONNECTION  
COMMUNICATIONS BETWEEN PERSONAL  
COMPUTER ANT PRINTING PERIPHERALS  
TRANSLATION CAPABILITY ALLOW  
OUTPUTS ON CABLE SIDE TO INTERFACE  
WITH 5V SIGNAL  
PULL-UP RESISTOR INTEGRATED ON ALL  
OPEN-DRAIN OUTPUT ELIMINATE THE  
NEED FOR DISCRETE RESISTOR  
REPLACE THE FUNCTION OF TWO  
74LVC1284 DEVICES  
DESCRIPTION  
The 74LVC161284 contains eight high speed non  
inverting bidirectional buffers and eleven control/  
status non-inverting buffers with open drain  
2
outputs fabricated in silicon gate C MOS  
technology. It’s intended to provide a standard  
signaling method for  
a bi-direction parallel  
peripheral in an Extended Capabilities Port Mode  
(ECP). The HD (Active HIGH) input pin enables  
the Cable port to switch from Open Drain to a high  
drive totem pole output, capable of sourcing 14mA  
on all thirteen buffer and 84mA on PERI LOGIC  
OUTPUT buffer. The DIR input determines the  
direction of data flow on the bidirectional buffers.  
DIR (Active HIGH) enables data flow from A port  
to B port. DIR (Active LOW) enables data flow  
from B port to A port. It is available in the  
commercial temperature range.  
May 2003  
1/11  

与74LVC161284TTR相关器件

型号 品牌 描述 获取价格 数据表
74LVC161BQ NEXPERIA Presettable synchronous 4-bit binary counter; asynchronous resetProduction

获取价格

74LVC161D NXP Presettable synchronous 4-bit binary counter; asynchronous reset

获取价格

74LVC161D NEXPERIA Presettable synchronous 4-bit binary counter; asynchronous resetProduction

获取价格

74LVC161D,118 NXP 74LVC161 - Presettable synchronous 4-bit binary counter; asynchronous reset SOP 16-Pin

获取价格

74LVC161DB NXP Presettable synchronous 4-bit binary counter; asynchronous reset

获取价格

74LVC161DB,112 NXP 74LVC161 - Presettable synchronous 4-bit binary counter; asynchronous reset SSOP1 16-Pin

获取价格