74ACT163M

更新时间： 2024-02-07 05:45:33

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		计数器
页数	文件大小	规格书
11页	100K
描述
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

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数据手册

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74ACT163M 数据手册

74ACT163

SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

■

HIGH SPEED:

f_MAX=200MHz (TYP.)atV_CC=5V

LOW POWER DISSIPATION:

I_CC=4 µA (MAX.) at T_A=25 ^oC

COMPATIBLEWITH TTL OUTPUTS

V_IH=2V (MIN), V_IL= 0.8V(MAX)

50Ω TRANSMISSIONLINEDRIVING

CAPABILITY

SYMMETRICAL OUTPUT IMPEDANCE:

|I_OH| = I_OL= 24 mA (MIN)

BALANCEDPROPAGATIONDELAYS:

t_PLHt_PHL

(Plastic Package)

(Micro Package)

ORDER CODES :

74ACT163B

74ACT163M

Enable Input (LOAD), Count Enable Input (PE)

and Count Enable Carry Input (TE), determine

the mode of operation as shown in the Truth

Table. A LOW signal on CLEAR overrides

counting and parallel loading and allows all

output to go LOW on the next rising edge of

CLOCK. A LOW signal on LOAD overrides

counting and allows information on Parallel Data

Qn inputs to be loaded into the flip-flops on the

next rising edge of CLOCK. With LOAD and

CLEAR, PE and TE permit counting when both

are HIGH. Conversely, a LOW signal on either

PE and TE inhibits counting.

The device is designed to interface directly High

Speed CMOS systems with TTL, NMOS and

CMOS output voltage levels.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

OPERATING VOLTAGERANGE:

V_CC(OPR)= 4.5V to 5.5V

PIN AND FUNCTION COMPATIBLEWITH

74 SERIES163

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The ACT163 is

high-speed CMOS

SYNCRONOUS PRESETTABLE COUNTER

fabricated with sub-micron silicon gate and

double-layer metal wiring C²MOS technology.It is

ideal for low power applications mantaining high

speed operation similar to eqivalent Bipolar

Schottky TTL. It is a 4 bit binary counter with

SynchronousClear.

The circuits have four fundamental modes of

operation, in order of preference: synchronous

reset, parallel load, count-up and hold. Four

control inputs, Master Reset (CLEAR), Parallel

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/11

December 1998

12 3 4 5 6 7...11

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