Datasheet > 74LS164

74LS164

更新时间： 2022-12-12 21:42:23

品牌	Logo	应用领域
SLS		移位寄存器
页数	文件大小	规格书
4页	40K
描述
8-Bit Serial-Input/Parallel-Output Shift Register

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数据手册

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74LS164 数据手册

SL74LS164

8-Bit Serial-Input/Parallel-Output

Shift Register

This 8-bit shift register features gated serial inputs and an

asynchronous reset. The gated serial inputs (A and B) permit complete

control over incoming data as a low at either (or both) input(s) inhibits

entry of the new data and resets the first flip flop to the low level at the

next clock pulse. A high level input enables the other input which will

then determine the state of the first flip-flop. Data at the serial inputs

may be changed while the clock is high or low, but only information

meeting the setup requirements will be entered clocking occurs or the

low-to-high level transition of the clock input. All inputs are diode-

clamped to minimize transmission-line effects.

ORDERING INFORMATION

SL74LS164N Plastic

SL74LS164D SOIC

T_A=0° to 70°C

Gated (Enable/Disable) Serial Inputs

Fully Buffered Clock and Serial Inputs

Asynchronous Clear

for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Clock

Outputs

Reset

A1 A2

X X

H D

D H

L L

Q_AQ_B... Q_H

L ... L

no change

D Q_An... Q_Gn

L Q_An... Q_Gn

PIN 14 =V_CC

PIN 7 = GND

D = data input

X = don’ t care

Q_An- Q_Gn= data shifted from the previous stage on a

rising edge at the clock input.

System Logic

Semiconductor

SLS

12 3 4

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