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591RB148M352DG PDF预览

591RB148M352DG

更新时间: 2024-01-13 21:31:53
品牌 Logo 应用领域
芯科 - SILICON 振荡器晶体振荡器石英晶振输出元件机械
页数 文件大小 规格书
12页 95K
描述
1 ps MAX JITTER CRYSTAL OSCILLATOR

591RB148M352DG 技术参数

生命周期:ActiveReach Compliance Code:unknown
风险等级:5.71其他特性:TRI-STATE; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; TR
最长下降时间:0.35 ns频率调整-机械:NO
频率稳定性:25%JESD-609代码:e4
安装特点:SURFACE MOUNT标称工作频率:148.352 MHz
最高工作温度:85 °C最低工作温度:-40 °C
振荡器类型:LVPECL输出负载:50 OHM
物理尺寸:7.0mm x 5.0mm x 1.8mm最长上升时间:0.35 ns
最大供电电压:2.75 V最小供电电压:2.25 V
标称供电电压:2.5 V表面贴装:YES
最大对称度:55/45 %端子面层:GOLD OVER NICKEL
Base Number Matches:1

591RB148M352DG 数据手册

 浏览型号591RB148M352DG的Datasheet PDF文件第2页浏览型号591RB148M352DG的Datasheet PDF文件第3页浏览型号591RB148M352DG的Datasheet PDF文件第4页浏览型号591RB148M352DG的Datasheet PDF文件第5页浏览型号591RB148M352DG的Datasheet PDF文件第6页浏览型号591RB148M352DG的Datasheet PDF文件第7页 
Si590/591  
1 ps MAX JITTER CRYSTAL OSCILLATOR (XO)  
(10 MHZ TO 525 MHZ)  
Features  
Available with any-rate output  
Available CMOS, LVPECL,  
LVDS, and CML outputs  
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
Pb-free/RoHS-compliant  
–40 to +85 ºC operating  
temperature range  
frequencies from 10 MHz to 525 MHz  
®
3rd generation DSPLL with superior  
jitter performance: 1 ps max jitter  
Better frequency stability than SAW-  
based oscillators  
Internal fundamental mode crystal  
ensures high reliability  
Ordering Information:  
Applications  
See page 6.  
SONET/SDH (OC-3/12/48)  
Networking  
SD/HD SDI/3G SDI video  
Test and measurement  
Storage  
FPGA/ASIC clock generation  
Pin Assignments:  
See page 5.  
Description  
®
(Top View)  
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry  
to provide a low jitter clock at high frequencies. The Si590/591 is available  
with any-rate output frequency from 10 to 525 MHz. Unlike a traditional XO,  
where a unique crystal is required for each output frequency, the Si590/591  
uses one fixed crystal to provide a wide range of output frequencies. This IC  
based approach allows the crystal resonator to provide exceptional  
frequency stability and reliability. In addition, DSPLL clock synthesis provides  
superior supply noise rejection, simplifying the task of generating low jitter  
clocks in noisy environments typically found in communication systems. The  
Si590/591 IC based XO is factory configurable for a wide variety of user  
specifications including frequency, supply voltage, output format, and  
temperature stability. Specific configurations are factory programmed at time  
of shipment, thereby eliminating long lead times associated with custom  
oscillators.  
VDD  
1
2
3
6
5
4
NC  
OE  
CLK–  
CLK+  
GND  
Si590 (LVDS/LVPECL/CML)  
VDD  
1
2
3
6
5
4
OE  
NC  
Functional Block Diagram  
NC  
VDD  
CLK– CLK+  
GND  
CLK  
Si590 (CMOS)  
17 k*  
VDD  
1
2
3
6
5
4
Any-rate  
10–525 MHz  
DSPLL®  
Clock  
Synthesis  
OE  
NC  
Fixed  
Frequency  
XO  
OE  
CLK–  
CLK+  
GND  
17 k*  
Si591 (LVDS/LVPECL/CML)  
*Note: Output Enable High/Low Options Available – See Ordering Information  
GND  
Preliminary Rev. 0.25 7/09  
Copyright © 2009 by Silicon Laboratories  
Si590/591  

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