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ACS8946T PDF预览

ACS8946T

更新时间: 2024-01-06 06:50:22
品牌 Logo 应用领域
商升特 - SEMTECH 开关ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式以太网
页数 文件大小 规格书
40页 663K
描述
Jitter Attenuating, Multiplying Phase Locked Loop, with Protection Switch, for OC-12/STM-4 and GbE

ACS8946T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN,针数:48
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.43Is Samacsys:N
应用程序:SONET;SDHJESD-30 代码:S-XQCC-N48
JESD-609代码:e3长度:7 mm
湿度敏感等级:1功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

ACS8946T 数据手册

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ACS8946 JAM PLL  
Jitter Attenuating, Multiplying Phase Locked Loop,  
with Protection Switch, for OC-12/STM-4 and GbE  
ADVANCED COMMUNICATIONS  
FINAL  
DATASHEET  
Introduction  
Features  
The ACS8946 JAM PLL is a Jitter-Attenuating, Multiplying  
differential Phase-Locked Loop, for generating low jitter  
output clocks compliant up to SONET OC-12 and STM-4  
622.08 MHz specifications. Its primary function is to  
clean up clock jitter for high performance optical line  
cards with OC-12 framers and serializers. It also provides  
reference switching functionality for line card protection,  
and frequency translation.  
‹ Meets rms jitter requirements of:  
‹ Telcordia GR-253[8] for OC-3 and OC-12  
‹ ITU-T G.813[4]/G.812[3] for STM-1 and STM-4 rates  
‹ ETSI EN300-462-7[1]/EN302-084[2] up to STM-16  
rates  
‹ PLL bandwidth and jitter peaking fully adjustable—  
supports PLL loop bandwidths from 2 kHz for superior  
input jitter filtering  
Typical output jitter generation is within OC-12/STM-4  
specifications, at 2.8 ps rms, making it an ideal dejittering  
solution for use with Semtech clock and line card parts:  
ACS8510, ACS8520, ACS8522 and ACS8530. The  
ACS8946 can also be used as a basic line card protection  
device in some applications.  
‹ Typical jitter generation down to:  
‹ 0.3 ps rms for 250 kHz to 5 MHz band for G.813,  
or EN300 462, at STM-4 (OC-12) rates  
‹ 2.8 ps rms for 12 kHz to 20 MHz band (against  
4.02 ps rms for GR-253-CORE at OC-48 rate)  
‹ ITU, ETSI and Telcordia frequency band results shows  
exceptional performance in a “Real World”  
The ACS8946 JAM PLL has two differential, frequency  
programmable, LVPECL reference inputs and one  
differential sync input. It has four outputs, programmable  
as LVPECL or CML, and frequency programmable to any  
common SONET/SDH rate i.e. 19.44 MHz, 38.88 MHz,  
77.76 MHz, 155.52 MHz, 311.04 MHz and 622.08 MHz.  
Jitter cleaning of Gigabit Ethernet (GbE) 125 MHz and  
156.25 MHz is also possible, with output frequency  
multiplication up to 625.00 MHz available.  
environment (low PLL bandwidth of 2 KHz and a  
typical input from an ACS8525 partner IC):  
‹ 0.4 ps rms for 250 kHz to 5 MHz band for G.813,  
or EN300 462, at STM-4 (OC-12) rates  
‹ 2.8 ps rms for 12 kHz to 20 MHz band  
‹ Tracking range ±400 ppm about a wide range of input  
frequencies  
‹ Manual or automatic control of reference selection  
‹ External feedback option  
‹ LOS alarms for each input, and for selected reference  
‹ 3.3 V operation, - 40 to +85°C temperature range  
‹ Small outline leadless 7 mm x 7 mm QFN48 package  
The device's operating bandwidth (and consequently the  
jitter attenuation point relating to this bandwidth) is fully  
configurable, and is set by external passive components.  
[1],[2], etc.  
Note...For items marked  
references are given in full  
‹ Lead (Pb)-free version available (ACS8946T),  
RoHS[11] and WEEE[12] compliant  
in the Reference Section on page 38.  
Block Diagram  
Figure 1 Simplified Block Diagram of the ACS8946 JAM PLL  
Loop  
Filter  
RESETB  
VC  
1 x CMOS  
Single-ended  
Sync Output  
1 x LVPECL  
Differential Sync Input  
Re-timing  
SYNC  
SYNC_OUT  
4 x LVPECL or CML  
Output Clocks,  
Independently  
Programmable  
from:  
2 x LVPECL  
Differential  
Input  
Selector  
CLK1  
CLK2  
Input References  
Programmable:  
19.44 MHz to  
156.25 MHz  
Frequency  
Dividers  
PFD  
Charge  
Pump  
2.5 GHz  
VCO  
Divider  
OUT[4:1]  
625.00 MHz  
622.08 MHz  
311.04 MHz  
155.52 MHz  
77.76 MHz  
Clock  
Drivers  
Device Configuration Select:  
CFG_IN[7:0]  
Control and Monitor  
38.88 MHz  
CFG_OUT2  
19.44 MHz  
Note: LOS alarm outputs are also  
used for device config. select  
125 MHz  
156.25 MHz  
Others Ethernet rates  
available using divider  
Clock Input Configuration for:  
- Manual selection  
- Auto Ref selection  
- External feedback mode  
(SEL_CLK2, AUTO_SEL)  
Lock Alarm (LOCKB)  
Frequency Select  
LOS Alarms for:  
- CLK1 (ALARM1_CO0)  
(RATE[2:1]A, RATE[2:1]B)  
- CLK2 (ALARM2_CO1)  
- Currently selected reference (ALARMC_CO3)  
F8946D_004Blockdiag_06  
Revision 3/November 2006 © Semtech Corp.  
Page1  
www.semtech.com  

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