ACS8522 SETS LITE
Synchronous Equipment Timing Source for
Stratum 3/4E/4 and SMC Systems
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Description
Features
The ACS8522 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8522 is fully
compliant with the required international specifications
and standards.
Suitable for Stratum 3, 4E, 4 and SONET Minimum
Clock (SMC) or SONET/SDH Equipment Clock (SEC)
applications (to Telcordia 1244-CORE[19] Stratum 3
and GR-253[17], and ITU-T G.813[11] Options Ι and ΙΙ
specifications)
Accepts four individual input reference clocks, all with
The device supports Free-run, Locked and Holdover
modes, with mode selection controlled either
automatically by an internal state machine or forced by
register configuration.
robust input clock source quality monitoring
Simultaneously generates four output clocks, plus two
Sync pulse outputs
Absolute Holdover accuracy better than 3 x 10-10
(manual), 7.5 x 10-14 (instantaneous); Holdover
stability defined by choice of external XO
The ACS8522 accepts up to four independent input SEC
reference clock sources from Recovered Line Clock, PDH
network, and Node Synchronization. The ACS8522
generates independent SEC and BITS clocks, an 8 kHz
Frame Synchronization clock and a 2 kHz Multi-Frame
Synchronization clock, both with programmable pulse
width and polarity.
Programmable PLL bandwidth, for wander and jitter
tracking/attenuation, 0.1 Hz to 70 Hz in 10 steps
Automatic hit-less source switchover on loss of input
Serial SPI compatible interface
The ACS8522 includes a Serial Port, which can be SPI
compatible, providing access to the configuration and
status registers for device setup.
Output phase adjustment in 6 ps steps up to ±200 ns
IEEE 1149.1[5] JTAG Boundary Scan
The ACS8522 supports IEEE 1149.1[5] JTAG boundary
scan.
Available in LQFP 64-pin package
The User can choose between OCXO or TCXO to define the
Stratum and/or Holdover performance required.
Single 3.3 V operation. 5 V tolerant
Lead (Pb)-free version available (ACS8522T), RoHS
Block Diagram
and WEEE compliant.
Figure 1 Block Diagram of the ACS8522 SETS LITE
Output O1: PECL/LVDS
Outputs O2 - 04: TTL
Programmable;
T4 DPLL/Freq. Synthesis
E1/DS1 (2.048/
1.544 MHz)
and frequency
multiples:
1.5 x, 2 x, 3 x
4 x, 6 x, 12 x
16 x and 24 x
E3/DS3
Output
Ports
T4 Output
APLL
Digital
Loop
Filter
PFD
DTO
Optional
Frequency
Dividers
O1
to
O4
T4 DPLL
Selector
Divider, 1/n
Inputs: 4 x TTL
Programmable;
2 kHz
4 kHz
N x 8 kHz
14
n = 1 to 2
Input
Port
Monitors
and
Selection
Control
2 kHz
8 kHz
and OC-N* rates
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
T0 DPLL/Freq. Synthesis
T0 Output
APLL
8 kHz
(FrSync)
2 kHz
4 x SEC
FrSync
&
MFrSync
Frequency
Dividers
Optional
T0 DPLL
Selector
Divider, 1/n
(MFrSync)
Digital
Loop
14
n = 1 to 2
PFD
DTO
Filter
T0 Feedback
APLL
OC-N* rates =
OC-1 51.84 MHz
OC-3 155.52 MHz
and derivatives:
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
TCK
TDI
TMS
TRST
TDO
Chip
Clock
Generator
IEEE
1149.1
JTAG
Priority
Table
Serial
Port
Register Set
77.76 MHz
155.52 MHz
311.04 MHz
OCXO or
TCXO
F8522P_001BLOCKDIA_04
Revision 5/November 2006 © Semtech Corp.
Page1
www.semtech.com