M390S2858DT1
PC133 Registered DIMM
M390S2858DT1 SDRAM DIMM
128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD
FEATURE
GENERAL DESCRIPTION
• Performance range
The Samsung M390S2858DT1 is a 128M bit x 72 Synchro-
nous Dynamic RAM high density memory module. The Sam-
sung M390S2858DT1 consists of eighteen CMOS Stacked
128Mx4 bit Synchronous DRAMs in two TSOP-II 400mil pack-
ages, three 18-bits Drive ICs for input control signal, one PLL
in 24-pin TSSOP package for clock and one 2K EEPROM in 8-
pin TSSOP package for Serial Presence Detect on a 168-pin
glass-epoxy substrate. Two 0.22uF and one 0.0022uF decou-
pling capacitors are mounted on the printed circuit board in
parallel for each SDRAM. The M390S2858DT1 is a Dual In-
line Memory Module and is intented for mounting into 168-pin
edge connector sockets.
Part No.
Max Freq. (Speed)
133MHz(7.5ns @ CL=2)
133MHz (7.5ns @ CL=3)
M390S2858DT1-C7C
M390S2858DT1-C7A
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4 , 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
• Serial presence detect with EEPROM
• PCB : Height (1,700mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
PIN NAMES
Pin
Pin Front Pin Front
Front Pin Back Pin Back Pin Back
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ CB7
CLK0
Function
Address input (Multiplexed)
Select bank
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
1
2
3
4
5
VSS
29 DQM1
DQ18 85
VSS
113 DQM5 141 DQ50
DQ0 30
DQ1 31
DQ2 32
DQ3 33
CS0
DU
VSS
A0
DQ19 86 DQ32 114 CS1 142 DQ51
Data input/output
Check bit (Data-in/data-out)
Clock input
VDD
87 DQ33 115 RAS 143
VDD
DQ20 88 DQ34 116
NC 89 DQ35 117
*VREF 90 118
*CKE1 91 DQ36 119
92 DQ37 120
DQ21 93 DQ38 121
VSS
A1
A3
A5
A7
A9
144 DQ52
145
NC
6
VDD
34
A2
VDD
146 *VREF
147 REGE
CKE0
Clock enable input
Chip select input
Row address strobe
Colume address strobe
Write enable
7
8
9
DQ4 35
DQ5 36
DQ6 37
A4
A6
A8
VSS
148
VSS
CS0 ~ CS3
RAS
149 DQ53
10
11
12
13
DQ7 38 A10/AP
DQ22 94 DQ39 122 BA0 150 DQ54
CAS
DQ8 39
40
DQ9 41
BA1
VDD
VDD
DQ23 95 DQ40 123
96 124
A11
VDD
151 DQ55
152
WE
VSS
VSS
VSS
VSS
DQ24 97 DQ41 125 *CLK1 153 DQ56
DQM0 ~ 7
VDD
DQM
14 DQ10 42 CLK0
DQ25 98 DQ42 126
DQ26 99 DQ43 127
A12
VSS
154 DQ57
155 DQ58
Power supply (3.3V)
Ground
15 DQ11 43
16 DQ12 44
17 DQ13 45
VSS
DU
CS2
VSS
72 DQ27 100 DQ44 128 CKE0 156 DQ59
73
74
75
76
77
78
79
80
81
82
VDD 101 DQ45 129 CS3 157
VDD
*VREF
Power supply for reference
Register enable
Serial data I/O
18
VDD
46 DQM2
DQ28 102 130 DQM6 158 DQ60
VDD
REGE
SDA
19 DQ14 47 DQM3
DQ29 103 DQ46 131 DQM7 159 DQ61
DQ30 104 DQ47 132 *A13 160 DQ62
20 DQ15 48
DU
VDD
NC
SCL
Serial clock
21
22
23
24
25
26
27
CB0
CB1
VSS
NC
NC
VDD
WE
49
50
51
52
53
54
DQ31 105 CB4 133
VDD
NC
NC
161 DQ63
162
163 *CLK3
NC
137 CB7 165 **SA0
138 166 **SA1
VSS
106 CB5 134
VSS
SA0 ~ 2
DU
Address in EEPROM
Don¢t use
NC
*CLK2 107
NC 108
VSS
NC
135
CB2
CB3
VSS
136 CB6 164
NC
No connection
*WP 109
**SDA 110
NC
VDD
VSS
*WP
Write protection
55 DQ16 83 **SCL 111 CAS 139 DQ48 167 **SA2
84
28 DQM0 56 DQ17
VDD 112 DQM4 140 DQ49 168
VDD
*
These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 0.0 Jan. 2002