Datasheet > AL2007LA

AL2007LA

更新时间： 2024-02-08 02:19:19

品牌	Logo	应用领域
三星 - SAMSUNG		/
页数	文件大小	规格书
16页	242K
描述
Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic structure

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技术参数
数据手册

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AL2007LA 技术参数

生命周期：	Obsolete	包装说明：	QFP, QFP48(UNSPEC)
Reach Compliance Code：	compliant	风险等级：	5.84
端子数量：	48	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP48(UNSPEC)
封装形式：	FLATPACK	电源：	3.3 V
认证状态：	Not Qualified	子类别：	PLL or Frequency Synthesis Circuits
最大供电电流 (Isup)：	3.5 mA	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子位置：	QUAD	Base Number Matches：	1

AL2007LA 数据手册

0.35µm 20MHZ-170MHZ FSPLL

AL2007LA

GENERAL DESCRIPTION

The AL2007LA is a Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic

structure. The PLL macrofunctions provide frequency multiplication capabilities.

The output clock frequency Fout is related to the reference input clock frequency Fin by the following equation:

Fout = ( m*Fin ) / ( p* 2S)

Where, Fout is the output clock frequency. Fin is the reference input clock frequency. m,p and s are the values for

programmable dividers. AL2007LA consists of a phase/Frequency Detector(PFD), a Charge Pump an External

Loop Filter, a Voltage Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as

shown in Figure1.

FEATURES

— 0.35um CMOS device technology

— 3.3 Volt Single power supply

— VCO frequency range: 60~170MHz

— Output frequency range: 20~170MHz

— Jitter ±150ps

— Duty ratio 40% to 60% at 170MHz

— Frequency changed by programmable divider

— Power down mode

IMPORTANT NOTICE

Please contact SEC application engineer to confirm the proper selection of M,P,S value.

FUNCTIONAL BLOCK DIAGRAM

Pre Divider

Charge

Pump

Loop

Filter

Fout

PFD

VCO

Post Scaler

Fin

(External)

Main Divider

Figure 1. Phase Lockd Loop Block Diagram

12 3 4 5 6 7...16

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