Datasheet
RX111 Group
R01DS0190EJ0100
Rev.1.00
Renesas MCUs
Jun 19, 2013
32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory,
USB 2.0 full-speed host/function/OTG, up to 6 comms channels,
12-bit A/D, 8-bit D/A, RTC
Features
PLQP0064KB-A 10 × 10 mm, 0.5 mm pitch
PLQP0064GA-A 14 × 14 mm, 0.8 mm pitch
PLQP0048KB-A 7 × 7 mm, 0.5 mm pitch
■ 32-bit RX CPU core
32 MHz maximum operating frequency
Capable of 50 DMIPS when operating at 32 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32-bit × 32-bit operations
Multiplication and division unit handles 32-bit × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
PWQN0048KB-A 7 × 7 mm, 0.50 mm pitch
PWQN0040KC-A 6 × 6 mm, 0.50 mm pitch
Fast interrupt
PWLG0064KA-A 5 × 5 mm, 0.5 mm pitch
PWLG0036KA-A 4 × 4 mm, 0.5 mm pitch
CISC Harvard architecture with five-stage pipeline
Variable-length instruction format, ultra-compact code
On-chip debugging circuit
■ Independent watchdog timer (IWDT)
■ Low power consumption functions
15-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
Operation from a single 1.8 to 3.6 V supply
Three low power consumption modes
■ On-chip functions for IEC 60730 compliance
■ On-chip flash memory for code, no wait states
Clock frequency accuracy measurement circuit, IWDT,
functions to assist in RAM testing, etc.
Operation at 32 MHz, read cycle of 31.25 ns
No wait states for reading at full CPU speed
16 to 128 Kbyte capacities
Programmable at 1.8 V
For instructions and operands
■ Up to six channels for communication
USB: USB 2.0 host (32 Kbyte or more ROM)/function/
On-The-Go (OTG) (one channel), full-speed = 12 Mbps,
low-speed = 1.5 Mbps, isochronous transfer, and BC
(Battery Charger) supported
SCI: Asynchronous mode, clock synchronous mode,
smart card interface (up to three channels)
I2C bus interface: Transfer at up to 400 kbps, capable of
SMBus operation (one channel)
■ On-chip data flash memory
8 Kbytes
1,000,000 Erase/Write cycles (typ.)
BGO (Background Operation)
■ On-chip SRAM, no wait states
8 to 16 Kbyte capacities
RSPI (one channel)
■ Data transfer controller (DTC)
■ Up to 8 extended-function timers
Four transfer modes
Transfer can be set for each interrupt source.
16-bit MTU: Input capture/output compare,
complementary PWM output, phase counting mode
(six channels)
■ Event link controller (ELC)
16-bit CMT (two channels)
Module operation can be initiated by event signals
without going through interrupts.
■ 12-bit A/D converter
Link operation between modules is possible while the
CPU is sleeping.
Up to 14 channels
1.0 μs minimum conversion speed
Double trigger (data duplication) function for motor
control
■ Reset and power supply voltage management
Six types including Power-On Reset (POR)
Low voltage detection (LVD) with voltage settings
■ 8-bit D/A converter
Two channels (for 64 pins only)
■ Clock functions
External clock input frequency: Up to 20 MHz
■ Temperature sensor
Main clock oscillator frequency: 1 to 20 MHz
Sub-clock oscillator frequency: 32.768 kHz
PLL circuit input: 4 to 8 MHz
Low-speed on-chip oscillator: 4 MHz
High-speed on-chip oscillator: 32 MHz
IWDT-dedicated on-chip oscillator: 15 kHz
Generate a dedicated 32.768-kHz clock for the RTC
On-chip clock frequency accuracy measurement circuit
(CAC)
■ General I/O ports
5-V tolerant, open drain, input pull-up
■ Multi-function pin controller (MPC)
Multiple I/O pins can be selected for peripheral functions.
■ Operating temperature range
40 to 85C
40 to 105°C
■ Realtime clock (RTC)
30-second, leap year, and error adjustment functions
Calendar count mode or binary count mode selectable
Capable of initiating exit from software standby mode
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
Page 1 of 107
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