Design Idea DI-37
™
DPA-Switch
16.5 W DC-DC Converter
Application
Device
Power Output
Input Voltage
Output Voltage
Topology
Telecom
DPA424R
16.5 W
36-75 VDC
3.3 V
Forward Sync. Rec.
Design Highlights
voltages and linearly reduces the maximum duty cycle with
input voltage to prevent core saturation during load transients.
Resistor R3 programs the DPA-Switch current limit to 60%
of nominal to limit fault and overload power. Drain voltage
clamping is provided by Zener diode VR1. Transformer core
reset is controlled by the gate capacitance of Q1.
•
•
•
•
•
Low cost
400 kHz synchronous rectification design
Low component count
Efficiency – 87% at 48 VDC
No current sense resistor or current transformer
required
Resistor R15 charges the gate of Q2, the forward synchronous
rectifier MOSFET. The catch synchronous rectifier MOSFET
(Q1) is directly driven by the transformer (T1) reset voltage and
operates only when Q2 is off. Diode D2 provides a conduction
path for the output inductor (L2) current when the transformer
reset is complete.
•
•
Output overload, open loop and thermal protection
Integrated UV meets ETSI standard
Operation
DPA-Switch greatly simplifies the design compared to a
discreteimplementation. ResistorR1programstheunder/over
C7
1 nF
R14
10 Ω
1.5 kV
L1
1 µH
2.5 A
C13
1 µF
0805
C10
C11
C12
+VIN
36-75 VDC
100 µF 100 µF 100 µF
L2
3.3 V, 5 A
6.3 V 6.3 V 6.3 V
R1
619 kΩ
1%
R15
10 Ω
D2
B540C
D1
BAV
Q1
Si4800
DY
19WS
RTN
T1
Q2
Si4800
DY
C4
4.7 µF
U2
R7
10 kΩ
20 V
R10
C1, C2
1 µF
3.24 kΩ
1%
100 V
DPA-Switch
C16
D3
U2
PC357N1T
100 nF
U1
D
L
BAV19WS
DPA424R
CONTROL
CONTROL
R6
150 Ω
R12
5.1 Ω
C
R9
220 Ω
S
X
F
C15
R4
C14
1 µF
10 µF
1.0 Ω
VR1
SMBJ
150
10 V
C5
220 nF
U3
C6
68 µF
10 V
R3
R11
LM431AIM3
11.1 kΩ
10.0 kΩ
VIN
1%
1%
PI-3650-072004
Figure 1. DPA424R–16.5 W, 3.3 V, 5 A DC-DC Converter.
July 2004
DI-37
www.powerint.com