Design Idea DI-25
DPA-Switch® 30 W DC-DC Converter
with Synchronous Rectification
Topology
Device
Power Output
Input Voltage
Output Voltage
Application
Forward
DC-DC Converter
30 W
36-75 VDC
DPA425R
5 V
DRAIN voltage clamping and core reset is provided by VR1
and the gate capacitance of Q1. The bias supply for U1 is
generated from an auxiliary winding on L2, providing higher
efficiency than a winding on T1.
Design Highlights
• Extremely low component count
• High Efficiency – 90% using synchronous rectification
• Accurate UV/OV allows self-driven synchronous
rectification
• No current sense resistor or current transformer required
• Output overload, open loop and thermal protection
• 300 kHz switching frequency – optimizes efficiency when
simple self-driven synchronous rectification is used
Capacitor C17 and R15 drive the gate of Q2, C17 providing DC
isolation to prevent Q1 gate overstress during power down.
Diode D4 resets the voltage on C17 before the next switching
cycle. Resistor R17 filters voltage spikes at the gate of Q1 and
D2 prevents the body diode of Q1 from conducting. MOSFETs
Q1 and Q2 are connected as self-driven synchronous rectifiers.
Operation
Key Design Points
DPA-Switchgreatlysimplifiesthedeisigncomparedtoadiscrete
implementation. Resistor R1 programs the input under/over
voltages to 33 V and 86 V, respectively, and linearly reduces the
maximumdutycyclewithinputvoltagetopreventcoresaturation
duringloadtransients. TighttolerancesoftheUV/OVthresholds
determinethesecondaryMOSFETsgatevoltagerange,allowing
low cost, self-driven synchronous rectification. Resistor R3
programs the internal current limit of the DPA425R to 45% of
nominal. The larger DPA-Switch selection reduces conduction
losses, raising efficiency without design or overload penalty.
• For nominal undervoltage set point VUV:
R1 = (VUV-2.35 V)/50 µA. VOV = (R1×135 µA) + 2.5 V.
• Select time constant of R16 and C17 to be much longer than
the period of one switching cycle.
• Zener VR1 safely limits the DRAIN voltage below BVDSS
and guarantees transformer reset.
• Opto U2 should have a CTR range of 100% to 200% for
optimum loop stability.
C7
1 nF
R14
10 Ω
1.5 kV
L1
1 µH
2.5 A
C10
100 µF 100 µF 1 µF
10 V 10 V
10 V
C11
C12
+
VIN
36-75 VDC
L2
5 V, 6 A
C17
3300 pF
R1
619 kΩ
1%
R15
10 Ω
R17
R16
10 kΩ
D1
D2
BAV
Q1
10 Ω
19WS
Si4888
DY
RTN
T1
Q2
Si4888
DY
D4
BAV19WS
C4
4.7 µF
20 V
U2
R7
10 kΩ
R10
C1, C2 & C3
1 µF
100 V
10.0 kΩ
1%
DPA-Switch
C16
D3
U2
PC357N1T
100 nF
U1
D
L
BAV19WS
DPA425R
CONTROL
R6
150 Ω
R12
5.1 Ω
C
R9
220 Ω
S
X
F
C13
R4
C14
1 µF
10 µF
10 V
1.0 Ω
VR1
SMBJ
150
R3
C5
220 nF
U3
C6
68 µF
10 V
18.2 kΩ
R11
LM431AIM3
1%
10.0 kΩ
VIN
1%
PI 3472 040903
Figure 1. DPA-Switch 30 W, 5 V, 6 A DC-DC Converter.
December 2004
DI-25
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