Datasheet > PLS101F

PLS101F

更新时间： 2024-02-27 10:35:02

品牌	Logo	应用领域
飞利浦 - PHILIPS		可编程逻辑
页数	文件大小	规格书
8页	127K
描述
OT PLD, PLA-Type, TTL, CDIP28

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技术参数
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PLS101F 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	DIP, DIP28,.6	Reach Compliance Code：	unknown
风险等级：	5.88	架构：	PLA-TYPE
JESD-30 代码：	R-XDIP-T28	JESD-609代码：	e0
输入次数：	16	输出次数：	8
产品条款数：	48	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	CERAMIC	封装代码：	DIP
封装等效代码：	DIP28,.6	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	5 V
可编程逻辑类型：	OT PLD	认证状态：	Not Qualified
子类别：	Programmable Logic Devices	标称供电电压：	5 V
表面贴装：	NO	技术：	TTL
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

PLS101F 数据手册

Philips Semiconductors Programmable Logic Devices

Product specification

Programmable logic arrays

(16 × 48 × 8)

PLS100/PLS101

DESCRIPTION

FEATURES

PIN CONFIGURATIONS

The PLS100 (3-State) and PLS101 (Open

Collector) are bipolar, fuse Programmable

Logic Arrays (PLAs). Each device utilizes the

standard AND/OR/Invert architecture to

directly implement custom sum of product

equations.

• Field-programmable (Ni-Cr link)

• Input variables: 16

N Package

FE*

• Output functions: 8

27 I8

• Product terms: 48

26 I9

Each device consists of 16 dedicated inputs

and 8 dedicated outputs. Each output is

capable of being actively controlled by any or

all of the 48 product terms. The True,

Complement, or Don’t Care condition of each

of the 16 inputs and be ANDed together to

comprise one P-term. All 48 P-terms can be

selectively ORed to each output.

• I/O propagation delay: 50ns (max.)

• Power dissipation: 600mW (typ.)

• Input loading: –100µA (max.)

• Chip Enable input

25 I10

24 I11

23 I12

I13

21 I14

I15

• Output option:

– PLS100: 3-State

19 CE

18 F0

17 F1

16 F2

15 F3

The PLS100 and PLS101 are fully TTL

compatible, and chip enable control for

expansion of input variables and output

inhibit. They feature either Open Collector or

3-State outputs for ease of expansion of

product terms and application in

– PLS101: Open-Collector

• Output disable function:

– 3-State: Hi-Z

– Open-Collector: High

GND 14

bus-organized systems.

Fuse Enable Pin: It is recommended that this pin

be left open or connected to ground during normal

operation.

Order codes are listed in the Ordering

Information Table.

APPLICATIONS

• CRT display systems

N = Plastic DIP (600mil-wide)

• Code conversion

• Peripheral controllers

• Function generators

• Look-up and decision tables

• Microprogramming

A Package

I5 I6 I7

I8 I9

28 27 26

I10

I11

I12

• Address mapping

• Character generators

• Data security encoders

• Fault detectors

I13

I14

I15

• Frequency synthesizers

• 16-bit to 8-bit bus interface

• Random logic replacement

12 13 14 15 16 17 18

GND

F1 F0

F5 F4

F3 F2

A = Plastic Leaded Chip Carrier

ORDERING INFORMATION

DESCRIPTION

3-STATE

PLS100N

PLS100A

OPEN COLLECTOR

PLS101N

DRAWING NUMBER

0413D

28-Pin Plastic Dual In-Line 600mil-wide

28-Pin Plastic Leaded Chip Carrier

PLS101A

0401F

October 22, 1993

853–0308 11164

12 3 4 5 6 7 8

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与PLS101F相关器件

型号	品牌	描述	获取价格	数据表
PLS101N	NXP	Programmable logic arrays 16 】 48 】 8	获取价格
PLS101N	YAGEO	OT PLD, 50ns, TTL, PDIP28	获取价格
PLS101N-B	ETC	Fuse-Programmable PLD	获取价格
PLS103A	PHILIPS	OT PLD, PAD-Type, TTL, PQCC28	获取价格
PLS103A	NXP	IC FPGA, PQCC28, Field Programmable Gate Array	获取价格
PLS103F	PHILIPS	OT PLD, PAD-Type, TTL, CDIP28	获取价格

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