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NE5537N PDF预览

NE5537N

更新时间: 2024-01-01 15:11:34
品牌 Logo 应用领域
恩智浦 - NXP 采样保持电路放大器放大器电路光电二极管
页数 文件大小 规格书
8页 107K
描述
Sample-and-hold amplifier

NE5537N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:MO-001包装说明:0.300 INCH, PLASTIC, MO-001, SOT-97-1, DIP-8
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.33.00.01
风险等级:5.89Is Samacsys:N
标称采集时间:20 µs放大器类型:SAMPLE AND HOLD CIRCUIT
最大模拟输入电压:11.5 V最小模拟输入电压:-11.5 V
JESD-30 代码:R-PDIP-T8长度:9.5 mm
湿度敏感等级:1负供电电压上限:-18 V
标称负供电电压 (Vsup):-15 V功能数量:1
端子数量:8最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP8,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):225电源:+-15 V
认证状态:Not Qualified采样并保持/跟踪并保持:SAMPLE
座面最大高度:4.2 mm子类别:Sample and Hold Circuits
最大压摆率:7.5 mA供电电压上限:18 V
标称供电电压 (Vsup):15 V表面贴装:NO
技术:BIFET温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

NE5537N 数据手册

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Philips Semiconductors Linear Products  
Product specification  
Sample-and-hold amplifier  
NE/SE5537  
DESCRIPTION  
PIN CONFIGURATIONS  
The NE5537 monolithic sample-and-hold amplifier combines the  
best features of ion-implanted JFETs with bipolar devices to obtain  
high accuracy, fast acquisition time, and low droop rate. This device  
is pin-compatible with the LF198, and features superior performance  
in droop rate and output drive capability. The circuit shown in Figure  
1 contains two operational amplifiers which function as a unity gain  
amplifier in the sample mode. The first amplifier has bipolar input  
transistors which give the system a low offset voltage. The second  
amplifier has JFET input transistors to achieve low leakage current  
from the hold capacitor. A unique circuit design for leakage current  
cancellation using current mirrors gives the NE5537 a low droop  
rate at higher temperature. The output stage has the capability to  
drive a 2kload. The logic input is compatible with TTL, PMOS or  
CMOS logic. The differential logic threshold is 1.4V with the sample  
mode occurring when the logic input is high. It is available in 8-lead  
TO-5, 8-pin plastic DIP packages, and 14-pin SO packages.  
FE and N Packages  
1
2
3
4
8
7
6
5
V+  
LOGIC  
OFFSET ADJUST  
LOGIC REFERENCE  
C
h
INPUT  
V–  
OUTPUT  
1
D Package  
1
14  
13  
12  
11  
10  
9
V
ADJ  
INPUT  
OS  
2
3
4
5
6
7
NC  
V+  
NC  
V–  
NC  
LOGIC  
LOGIC REFERENCE  
NC  
NC  
NC  
FEATURES  
Operates from ±5V to ±18V supplies  
8
C
h
OUTPUT  
NOTE:  
Hold leakage current 6pA @ T = 25°C  
J
1. SO and non-standard pinouts.  
Less than 4µs acquisition time  
TTL, PMOS, CMOS compatible logic input  
0.5mV typical hold step at CH=0.01µF  
Low input offset: 1MV (typical)  
BLOCK DIAGRAM  
OFFSET  
2
0.002% gain accuracy with R =2kΩ  
L
30k  
Low output noise in hold mode  
5
Input characteristics do not change during hold mode  
High supply rejection ratio in sample or hold  
Wide bandwidth  
OUTPUT  
3
+
INPUT  
8
LOGIC  
300  
7
+
LOGIC  
REFERENCE  
6
HOLD  
CAPACITOR  
ORDERING INFORMATION  
DESCRIPTION  
TEMPERATURE RANGE  
0 to +70°C  
ORDER CODE  
NE5537N  
DWG #  
8-Pin Plastic Dual In-Line Package (DIP)  
14-Pin Plastic Small Outline (SO) Package  
8-Pin Plastic Dual In-Line Package (DIP)  
0404B  
0175D  
0404B  
0 to +70°C  
NE5537D  
-55°C to +125°C  
SE5537FE  
884  
August 31, 1994  
853-1044 13721  

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