Datasheet > 存储 > DRAM> CBTV4020EE/G

CBTV4020EE/G

更新时间： 2024-02-10 11:10:25

品牌	Logo	应用领域
恩智浦 - NXP		动态存储器双倍数据速率
页数	文件大小	规格书
16页	98K
描述
IC DDR DRAM, PDSO72, 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, TFBGA-72, Dynamic RAM

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技术参数
数据手册

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CBTV4020EE/G 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	FBGA, BGA72,10X10,20	Reach Compliance Code：	unknown
风险等级：	5.84	JESD-30 代码：	S-PBGA-B72
逻辑集成电路类型：	BUS DRIVER	端子数量：	72
最高工作温度：	85 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	FBGA
封装等效代码：	BGA72,10X10,20	封装形状：	SQUARE
封装形式：	GRID ARRAY, FINE PITCH	电源：	2.5 V
认证状态：	Not Qualified	子类别：	Bus Driver/Transceivers
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
温度等级：	OTHER	端子形式：	BALL
端子节距：	0.5 mm	端子位置：	BOTTOM
Base Number Matches：	1

CBTV4020EE/G 数据手册

CBTV4020

20-bit DDR SDRAM 2 : 1 MUX

Rev. 03 — 4 April 2008

Product data sheet

1. General description

This 20-bit bus switch is designed for 2.3 V to 2.7 V V_DDoperation and SSTL_2 select

input levels.

Each host port pin is multiplexed to one of two DIMM port pins. When the SEL pin is HIGH

the A DIMM port is turned on and the B DIMM port is off. The ON-state connects the host

port to the DIMM port through a 20 Ω nominal series resistance. When the port is off a

high-impedance state exists between the Host and disabled DIMM. The DIMM port is

terminated with a 100 Ω resistor to ground. When the SEL pin is LOW the B DIMM port is

turned on and the A DIMM port is off.

The part incorporates a very low crosstalk design. It has a very low skew between outputs

(< 50 ps) and low skew (< 50 ps) for rising and falling edges. The part has optimal

performance in DDR data bus applications.

Each switch has been optimized for connection to 1-bank or 2-bank DIMMs.

The low internal RC time constant of the switch (20 Ω × 7 pF) allows data transfer to be

made with minimal propagation delay.

The CBTV4020 is characterized for operation from 0 °C to +85 °C.

2. Features

I SEL signal is SSTL_2 compatible

I Optimized for use in Double Data Rate (DDR) SDRAM applications

I Designed to be used with 400 Mbit/s 200 MHz DDR data bus

I Switch ON resistance is designed to eliminate the need for series resistor to DDR

SDRAM

I R_ON~ 20 Ω

I Internal 100 Ω pull-down resistors on DIMM side when path is disabled

I Low differential skew

I Matched rise/fall slew rate

I Low crosstalk

I One DIMM select control line

I Latch-up protection exceeds 500 mA per JESD78

I ESD protection exceeds 1500 V HBM per JESD22-A114, 200 V MM per

JESD22-A115 and 1000 V CDM per JESD22-C101

12 3 4 5 6 7...16

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