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74AUP2G00GM PDF预览

74AUP2G00GM

更新时间: 2024-02-06 20:24:33
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
16页 84K
描述
Low-power dual 2-input NAND gate

74AUP2G00GM 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HVBCC,Reach Compliance Code:compliant
Factory Lead Time:13 weeks风险等级:1.77
系列:AUP/ULP/VJESD-30 代码:R-PBCC-B8
长度:1.35 mm逻辑集成电路类型:NAND GATE
功能数量:2输入次数:2
端子数量:8最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVBCC封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):24.9 ns座面最大高度:0.35 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.1 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:BUTT端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:0.8 mm

74AUP2G00GM 数据手册

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74AUP2G00  
Low-power dual 2-input NAND gate  
Rev. 01 — 25 August 2006  
Product data sheet  
1. General description  
The 74AUP2G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device,  
superior to most advanced CMOS compatible TTL families.  
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall  
times across the entire VCC range from 0.8 V to 3.6 V.  
This device ensures a very low static and dynamic power consumption across the entire  
VCC range from 0.8 V to 3.6 V.  
This device is fully specified for partial Power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
The 74AUP2G00 provides the dual 2-input NAND function.  
2. Features  
Wide supply voltage range from 0.8 V to 3.6 V  
High noise immunity  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114-D Class 3A exceeds 4000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101-C exceeds 1000 V  
Low static power consumption; ICC = 0.9 µA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C  

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