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74AUP1G885DC PDF预览

74AUP1G885DC

更新时间: 2024-01-02 08:24:55
品牌 Logo 应用领域
恩智浦 - NXP 栅极逻辑集成电路石英晶振光电二极管
页数 文件大小 规格书
19页 71K
描述
Low-power dual function gate

74AUP1G885DC 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:VSON,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.63
Is Samacsys:N系列:AUP/ULP/V
JESD-30 代码:R-PDSO-N8JESD-609代码:e3
长度:1.95 mm逻辑集成电路类型:XOR GATE
湿度敏感等级:1功能数量:2
输入次数:3端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):23.7 ns
认证状态:Not Qualified座面最大高度:0.5 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.1 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1 mm
Base Number Matches:1

74AUP1G885DC 数据手册

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74AUP1G885  
Low-power dual function gate  
Rev. 01.00 — 26 January 2006  
Preliminary data sheet  
1. General description  
The 74AUP1G885 is a high-performance, low-power, low-voltage, Si-gate CMOS device,  
superior to most advanced CMOS compatible TTL families.  
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall  
times across the entire VCC range from 0.8 V to 3.6 V.  
This device ensures a very low static and dynamic power consumption across the entire  
VCC range from 0.8 V to 3.6 V.  
This device is fully specified for partial Power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
The 74AUP1G885 provides two functions in one device.The output state of the outputs  
(1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the boolean  
funtion: 1Y = A × C. The output 2Y provides the boolean funtion: 2Y = A × B + A × C  
2. Features  
Wide supply voltage range from 0.8 V to 3.6 V  
High noise immunity  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114-C Class 3A exceeds 4000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101-C exceeds 1000 V  
Low static power consumption; ICC = 0.9 µA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C  

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