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74AUP1G04GF PDF预览

74AUP1G04GF

更新时间: 2024-01-02 15:29:25
品牌 Logo 应用领域
恩智浦 - NXP 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
16页 82K
描述
Low-power inverter

74AUP1G04GF 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:TSSOP, TSSOP5/6,.08Reach Compliance Code:unknown
风险等级:5.8JESD-30 代码:R-PDSO-G5
JESD-609代码:e0负载电容(CL):30 pF
逻辑集成电路类型:INVERTER最大I(ol):0.0017 A
端子数量:5最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP5/6,.08
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:1.2/3.3 V
Prop。Delay @ Nom-Sup:20.9 ns认证状态:Not Qualified
施密特触发器:NO子类别:Gates
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUALBase Number Matches:1

74AUP1G04GF 数据手册

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74AUP1G04  
Low-power inverter  
Rev. 02 — 28 June 2006  
Product data sheet  
1. General description  
The 74AUP1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device,  
superior to most advanced CMOS compatible TTL families.  
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall  
times across the entire VCC range from 0.8 V to 3.6 V.  
This device ensures a very low static and dynamic power consumption across the entire  
VCC range from 0.8 V to 3.6 V.  
This device is fully specified for partial Power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
The 74AUP1G04 provides the single inverting buffer.  
2. Features  
Wide supply voltage range from 0.8 V to 3.6 V  
High noise immunity  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114-C Class 3A. Exceeds 5000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101-C exceeds 1000 V  
Low static power consumption; ICC = 0.9 µA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C  

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