NTHS2101P
Power MOSFET
−8.0 V, −7.5 A P−Channel ChipFETt
Features
• Offers an Ultra Low R
Solution in the ChipFET Package
DS(on)
http://onsemi.com
• Miniature ChipFET Package 40% Smaller Footprint than TSOP−6
making it an Ideal Device for Applications where Board Space is at a
Premium
V
Ultra Low R
TYP
I MAX
D
(BR)DSS
DS(on)
• Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin
Environments such as Portable Electronics
19 mW @ −4.5 V
25 mW @ −2.5 V
34 mW @ −1.8 V
GS
−8.0 V
−7.5 A
GS
GS
• Designed to Provide Low R
at Gate Voltage as Low as 1.8 V, the
DS(on)
Operating Voltage used in many Logic ICs in Portable Electronics
• Simplifies Circuit Design since Additional Boost Circuits for Gate
Voltages are not Required
S
• Operated at Standard Logic Level Gate Drive, Facilitating Future
Migration to Lower Levels using the same Basic Topology
• Pb−Free Package is Available
G
Applications
• Optimized for Battery and Load Management Applications in
Portable Equipment such as MP3 Players, Cell Phones, Digital
Cameras, Personal Digital Assistant and other Portable Applications
D
P−Channel MOSFET
• Charge Control in Battery Chargers
• Buck and Boost Converters
ChipFET
CASE 1206A
STYLE 1
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
V
−8.0
V
DSS
dc
MARKING
DIAGRAM
PIN
CONNECTIONS
Gate−to−Source Voltage − Continuous
V
"8.0
V
GS
dc
Drain Current
− Continuous
− 5 seconds
I
−5.4
−7.5
A
D
8
7
6
5
1
2
3
4
D
D
D
S
D
D
D
G
1
2
3
4
8
7
6
5
Total Power Dissipation
Continuous @ T = 25°C
P
W
D
1.3
2.5
0.7
1.3
A
(5 sec) @ T = 25°C
A
Continuous @ 85°C
(5 sec) @ 85°C
Continuous Source Current
Thermal Resistance (Note 1)
Is
−1.1
A
D4 = Specific Device Code
M = Month Code
R
°C/W
q
JA
Junction−to−Ambient, 5 sec
Junction−to−Ambient, Continuous
50
95
ORDERING INFORMATION
†
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
T
260
°C
Device
Package
Shipping
L
NTHS2101PT1
NTHS2101PT1G
ChipFET
3000/Tape & Reel
3000/Tape & Reel
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
ChipFET
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
October, 2004 − Rev. 4
NTHS2101P/D