N01L83W2A
1Mb Ultra-Low Power Asynchronous CMOS SRAM
128K × 8 bit
Overview
Features
The N01L83W2A is an integrated memory device
containing a 1 Mbit Static Random Access Memory
organized as 131,072 words by 8 bits. The device
is designed and fabricated using ON
• Single Wide Power Supply Range
2.3 to 3.6 Volts
• Very low standby current
2.0µA at 3.0V (Typical)
Semiconductor’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with two chip enable
(CE1 and CE2) controls and output enable (OE) to
allow for easy memory expansion. The
• Very low operating current
2.0mA at 3.0V and 1µs (Typical)
• Very low Page Mode operating current
0.8mA at 3.0V and 1µs (Typical)
N01L83W2A is optimal for various applications
where low-power is critical such as battery backup
and hand-held devices. The device can operate
• Simple memory control
Dual Chip Enables (CE1and CE2)
Output Enable (OE) for memory expansion
o
over a very wide temperature range of -40 C to
• Low voltage data retention
o
+85 C and is available in JEDEC standard
Vcc = 1.8V
packages compatible with other standard 128Kb x
8 SRAMs.
• Very fast output enable access time
30ns OE access time
• Automatic power down to standby mode
• TTL compatible three-state output driver
Product Family
Standby
Power
Supply
(Vcc)
Operating
Current (Icc),
Typical
Operating
Current (ISB),
Part Number
Package Type
Speed
Temperature
Typical
N01L83W2AT
N01L83W2AN
N01L83W2AT2
N01L83W2AN2
32 - TSOP I
32 - STSOP I
55ns @ 2.7V
70ns @ 2.3V
-40oC to +85oC
2.3V - 3.6V
2 µA
2 mA @ 1MHz
32 -TSOP I Green
32 - STSOP I Green
Pin Configuration
Pin Descriptions
Pin Name
A0-A16
WE
CE1, CE2
OE
Pin Function
OE
A11
A9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
2
Address Inputs
Write Enable Input
Chip Enable Input
Output Enable Input
Data Inputs/Outputs
Power
Ground
Not Connected
A8
3
A13
WE
CE2
A15
VCC
4
5
6
32-Pin
STSOP-I
TSOP-I
7
8
9
NC
A16
A14
A12
A7
I/O0-I/O7
I/O2
I/O1
I/O0
A0
10
11
12
13
14
15
16
VCC
VSS
NC
A1
A6
A2
A5
A3
A4
©2008 SCILLC. All rights reserved.
July 2008 - Rev. 10
Publication Order Number:
N01L83W2A/D