N01L63W2A
1Mb Ultra-Low Power Asynchronous CMOS SRAM
64K × 16 bit
Features
• Single Wide Power Supply Range
2.3 to 3.6 Volts
Overview
The N01L63W2A is an integrated memory device
containing a 1 Mbit Static Random Access Memory
organized as 65,536 words by 16 bits. ON
Semiconductor’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with two chip enable
(CE1 and CE2) controls and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB and LB) allow the upper and lower bytes to be
accessed independently and can also be used to
deselect the device. The N01L63W2A is optimal
for various applications where low-power is critical
such as battery backup and hand-held devices.
The device can operate over a very wide
• Very low standby current
2.0µA at 3.0V (Typical)
• Very low operating current
2.0mA at 3.0V and 1µs (Typical)
• Very low Page Mode operating current
0.8mA at 3.0V and 1µs (Typical)
• Simple memory control
Dual Chip Enables (CE1and CE2)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.8V
• Very fast output enable access time
o
o
30ns OE access time
temperature range of -40 C to +85 C and is
available in JEDEC standard packages compatible
with other standard 64Kb x 16 SRAMs.
• Automatic power down to standby mode
• TTL compatible three-state output driver
• Compact space saving BGA package avail-
able
Product Family
Standby
Current
Power
Supply
(Vcc)
Operating
Current (Icc),
Typical
Operating
Part Number
Package Type
Speed
Temperature
(ISB), Typical
N01L63W2AB
N01L63W2AT
N01L63W2AB2
N01L63W2AT2
48 - BGA
44 - TSOP II
55ns @ 2.7V
70ns @ 2.3V
-40oC to +85oC
2.3V - 3.6V
2 µA
2 mA @ 1MHz
48 - BGA Green
44 - TSOP II Green
Pin Configuration
Pin Descriptions
1
2
3
A0
4
A1
5
A2
6
A4
1
PIN
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A3
2
ONE
A6
A2
3
LB
OE
CE2
A7
A
B
C
D
E
F
Pin Name
A0-A15
WE
CE1, CE2
OE
LB
UB
I/O0-I/O15
Pin Function
A1
4
OE
A0
5
UB
I/O8
A3
A4
A6
A7
NC
I/O0
UB
CE1
CE1
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
6
Address Inputs
Write Enable Input
Chip Enable Input
LB
7
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
CE2
A8
I/O9 I/O10 A5
I/O1 I/O2
I/O3 VCC
I/O4 VSS
8
9
VSS I/O11
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
VCC I/O12
I/O14 I/O13 A14
NC
A15 I/O5 I/O6
I/O15
NC
A12
A9
A13
A10
I/O7
NC
NC
A8
WE
A11
G
H
A9
VCC
VSS
NC
Power
Ground
Not Connected
A10
A11
48 Pin BGA (top)
6 x 8 mm
NC
©2008 SCILLC. All rights reserved.
July 2008 - Rev. 9
Publication Order Number:
N01L63W2A/D
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