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JLC1562B PDF预览

JLC1562B

更新时间: 2024-02-16 15:34:01
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
10页 83K
描述
I2C Bus I/O Expander

JLC1562B 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:PLASTIC, DIP-16针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.73
Is Samacsys:NJESD-30 代码:R-PDIP-T16
JESD-609代码:e3长度:19.175 mm
I/O 线路数量:8端口数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:4.44 mm
最大供电电压:6 V最小供电电压:4.2 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.62 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

JLC1562B 数据手册

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JLC1562B  
I2C Bus I/O Expander  
2
The JLC1562B facilitates easy I C Bus expandibility. Multiple  
2
devices (up to 8 on the same I C Bus) are easily added as each device  
has its own selectable 3−bit address. The JLC1562B provides an 8−bit  
bidirectional input/output port and 6−bit resolution Digital to Analog  
Converter. The voltage on pins P0−P4 is compared with a controllable  
http://onsemi.com  
2
threshold voltage and the results are readable through the I C Bus.  
2
I C Bus interface pins SDA, SCL and A0−A2 are; Serial Data,  
MARKING  
DIAGRAMS  
Serial Clock and Device Address respectively. External interface pins  
are P0−P7 and VDAC; I/O Port and D/A output.  
16  
PDIP−16  
N SUFFIX  
Features  
JLC1562BN  
AWLYYWW  
Pb−Free Packages are Available*  
Low Power Dissipation  
CASE 648  
1
2
I C−Bus Format (2−Wire Type; SDA, SCL) Data Transfer  
16  
6−bit DAC  
Bus Address Selectable (3−bit)  
Address Input Pins are Pulled Up to V with Internal Resistor  
I/O Pins are Open Drain Outputs  
5 Comparators at Inputs  
Inputs Protected from External Bus Currents in Power Down Mode  
EIAJ−16  
F SUFFIX  
CASE 966  
JLC1562B  
ALYW  
DD  
1
A
= Assembly Location  
WL, L = Wafer Lot  
YY, Y = Year  
WW, W = Work Week  
A0  
A1  
A2  
P0  
P1  
P2  
P3  
1
2
3
4
5
6
7
8
16  
V
DD  
15 SDA  
14 SCL  
13 VDAC  
12 P7  
ORDERING INFORMATION  
Device  
Package  
Shipping  
JLC1562BN  
PDIP−16  
500 / Unit PAK  
500 / Unit PAK  
11 P6  
JLC1562BNG  
PDIP−16  
10 P5  
(Pb−Free)  
V
SS  
9
P4  
JLC1562BF  
EIAJ−16  
50 Units / Rail  
(Pb−Free)  
JLC1562BFEL  
EIAJ−16  
(Pb−Free)  
2000 Units / Reel  
Figure 1. Pin Assignment  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specifications  
Brochure, BRD8011/D.  
PIN LIST  
A0−A2  
Chip Address Input  
P0−P4  
P5−P7  
SCL  
Comparator Input / Open Drain Output  
Comparator Input / Open Drain Output  
Serial Clock Input  
2
SDA  
I C Data Output  
VDAC  
DAC Output  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
July, 2004 − Rev. 4  
JLC1562B/D  

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