Datasheet > 驱动程序和接口 > MOSFET 驱动器> CS7054YN14

CS7054YN14

更新时间： 2024-02-19 16:52:41

品牌	Logo	应用领域
安森美 - ONSEMI		驱动器 MOSFET驱动器驱动程序和接口接口集成电路光电二极管控制器
页数	文件大小	规格书
12页	91K
描述
Low Side PWM FET Controller

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CS7054YN14 技术参数

生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	14
Reach Compliance Code：	unknown	风险等级：	5.75
高边驱动器：	YES	接口集成电路类型：	BUFFER OR INVERTER BASED MOSFET DRIVER
JESD-30 代码：	R-PDIP-T14	长度：	18.86 mm
功能数量：	1	端子数量：	14
最高工作温度：	125 °C	最低工作温度：	-40 °C
标称输出峰值电流：	0.4 A	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	COMMERCIAL
座面最大高度：	4.69 mm	最大供电电压：	16 V
最小供电电压：	8 V	标称供电电压：	12 V
表面贴装：	NO	温度等级：	AUTOMOTIVE
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	宽度：	7.62 mm
Base Number Matches：	1

CS7054YN14 数据手册

CS7054

Low Side PWM FET

Controller

The CS7054 is a monolithic integrated circuit designed primarily to

control the rotor speed of permanent magnet, direct current (DC)

brush motors. It drives the gate of an N channel power MOSFET or

IGBT with a user–adjustable, fixed frequency, variable duty cycle,

pulse width modulated (PWM) signal. The CS7054 can also be used to

control other loads such as incandescent bulbs and solenoids.

Inductive current from the motor or solenoid is recirculated through an

external diode.

http://onsemi.com

DIP–14

N SUFFIX

CASE 646

The CS7054 accepts a DC level input signal of 0 to 5.0 V to control

the pulse width of the output signal. This signal can be generated by a

potentiometer referenced to the on–chip 5.0 V linear regulator, or a

filtered 0% to 100% PWM signal also referenced to the 5.0 V

regulator.

The IC is placed in a sleep state by pulling the CTL lead below 0.5 V.

In this mode everything on the chip is shut down except for the

on–chip regulator and the overall current draw is less than 275 µA.

There are a number of on–chip diagnostics that look for potential

failure modes and can disable the external power MOSFET.

SO–16L

DW SUFFIX

CASE 751G

PIN CONNECTIONS AND

MARKING DIAGRAMS

OUTPUT

GND

PGND

INH

Features

FLT

• 200 mA Peak PWM Gate Drive Output

OSC

ADJ

• Patented Voltage Compensation Circuit

• 100% Duty Cycle Capability

• 5.0 V, ± 3.0% Linear Regulator

• Low Current Sleep Mode

OSC

SENSE+

CTL

SENSE–

REG

DIP–14

• Overvoltage Protection

• Overcurrent Protection of External MOSFET/IGBT

• Output Inhibit

OUTPUT

GND

FLT

PGND

INH

OSC

CTL

OSC

ADJ

SENSE+

SENSE–

REG

SO–16L

WL, L

YY, Y

= Assembly Location

= Wafer Lot

= Year

WW, W = Work Week

ORDERING INFORMATION

Device

Package

Shipping

CS7054YN14

25 Units/Rail

46 Units/Rail

DIP–14

SO–16L

CS7054YDW16

CS7054YDWR16

1000 Tape & Reel

Semiconductor Components Industries, LLC, 2001

Publication Order Number:

January, 2001 – Rev. 12

CS7054/D

12 3 4 5 6 7...12

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