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ADP3118JCPZ-RL

更新时间: 2024-01-12 22:01:58
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器MOSFET驱动器驱动程序和接口接口集成电路
页数 文件大小 规格书
14页 221K
描述
Dual Bootstrapped 12 V MOSFET Driver with Output Disable

ADP3118JCPZ-RL 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:SOIC包装说明:SOP,
针数:8Reach Compliance Code:unknown
风险等级:5.74高边驱动器:YES
接口集成电路类型:HALF BRIDGE BASED MOSFET DRIVERJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
湿度敏感等级:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:1.75 mm
最大供电电压:13.2 V最小供电电压:4.15 V
标称供电电压:12 V表面贴装:YES
温度等级:OTHER端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.9 mmBase Number Matches:1

ADP3118JCPZ-RL 数据手册

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Dual Bootstrapped 12 V  
MOSFET Driver with Output Disable  
ADP3118  
FEATURES  
GENERAL DESCRIPTION  
Optimized for low gate charge MOSFETs  
All-in-one synchronous buck driver  
Bootstrapped high-side drive  
One PWM signal generates both drives  
Anticross-conduction protection circuitry  
Output disable control turns off both MOSFETs to float  
output per Intel VRM 10  
The ADP3118 is a dual, high voltage MOSFET driver optimized  
for driving two N-channel MOSFETs, which are the two switches  
in a nonisolated synchronous buck power converter. Each of the  
drivers is capable of driving a 3000 pF load with a 25 ns prop-  
agation delay and a 25 ns transition time. One of the drivers can  
be bootstrapped and is designed to handle the high voltage slew  
rate associated with floating high-side gate drivers. The ADP3118  
includes overlapping drive protection to prevent shoot-through  
current in the external MOSFETs.  
Meets CPU VR requirement when used with  
Analog Devices, Inc. Flex-Mode1 controller  
The OD pin shuts off both the high-side and the low-side  
MOSFETs to prevent rapid output capacitor discharge during  
system shutdown.  
APPLICATIONS  
Multiphase desktop CPU supplies  
Single-supply synchronous buck converters  
The ADP3118 is specified over the commercial temperature  
range of 0°C to 85°C and is available in 8-lead SOIC and 8-lead  
LFCSP packages.  
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM  
V
12V  
IN  
D1  
VCC  
4
BST  
ADP3118  
1
8
C
BST2  
C
BST1  
2
R
G
IN  
DRVH  
Q1  
DELAY  
R
BST  
TO  
INDUCTOR  
SW  
7
CMP  
VCC  
6
CMP  
DRVL  
PGND  
1V  
CONTROL  
LOGIC  
5
6
Q2  
DELAY  
3
OD  
Figure 1.  
1Flex-Mode™ is protected by U.S. Patent 6683441.  
©2008 SCILLC. All rights reserved.  
January 2008 – Rev. 2  
Publication Order Number:  
ADP3118/D  

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