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0W344-004-XTP PDF预览

0W344-004-XTP

更新时间: 2024-02-16 23:46:56
品牌 Logo 应用领域
安森美 - ONSEMI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
43页 1433K
描述
1.0 Genral Description

0W344-004-XTP 技术参数

是否无铅: 不含铅生命周期:End Of Life
零件包装代码:QFN包装说明:HQCCN, LCC52,.31SQ,20
针数:52Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.74地址总线宽度:
桶式移位器:YES位大小:16
边界扫描:NO最大时钟频率:33 MHz
外部数据总线宽度:格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:S-XQCC-N52
JESD-609代码:e3长度:8 mm
低功率模式:NO湿度敏感等级:3
端子数量:52最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HQCCN封装等效代码:LCC52,.31SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.25 V
认证状态:Not QualifiedRAM(字数):8192
座面最大高度:1.1 mm子类别:Digital Signal Processors
最大供电电压:1.8 V最小供电电压:1.03 V
标称供电电压:1.25 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, MIXEDBase Number Matches:1

0W344-004-XTP 数据手册

 浏览型号0W344-004-XTP的Datasheet PDF文件第2页浏览型号0W344-004-XTP的Datasheet PDF文件第3页浏览型号0W344-004-XTP的Datasheet PDF文件第4页浏览型号0W344-004-XTP的Datasheet PDF文件第5页浏览型号0W344-004-XTP的Datasheet PDF文件第6页浏览型号0W344-004-XTP的Datasheet PDF文件第7页 
BelaSigna 200  
1.0 General Description  
BelaSigna 200 is  
a high-performance, programmable, mixed-signal digital signal processor (DSP) that is based on  
ON Semiconductor’s patented second-generation SignaKlara™ technology.  
This single-chip solution is ideally suited for embedded applications where audio performance, low power consumption and  
miniaturization are critical. BelaSigna 200 targets a wide variety of digital speech- and audio-centric applications, including:  
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Communication headsets  
Smart phones  
Personal digital assistants (PDAs)  
Hands-free car kits  
Bluetooth™ wireless technology systems  
BelaSigna 200 provides numerous analog and digital interfaces including parallel, serial, synchronous, and asynchronous interfaces to  
facilitate the connection with transducers from various applications.  
BelaSigna 200 contains two primary processing blocks, which all work together to provide a complete audio processing chain. The  
analog section includes two 16-bit A/D converters and two 16-bit D/A converters. Two on-chip direct digital output stages allow  
BelaSigna 200 to drive various output transducers directly, eliminating the need for external power amplifiers.  
BelaSigna 200 features internal clock generation and power regulation for excellent noise and power performance. Two DSP  
subsystems operate concurrently: the RCore, which is a fully programmable DSP core, and the weighted overlap-add (WOLA)  
filterbank coprocessor, which is a dedicated, configurable processor that executes time-frequency domain transforms and other vector-  
based computations. In addition to these processors, there are several other peripherals, which optimize the architecture to audio  
processing, such as the onput/output processor (IOP) – an audio-targeted direct memory access (DMA) processor, which runs in the  
background and manages the data flow between the converters and the two processors. The BelaSigna 200 functional block diagram is  
shown in Figure 1.  
Figure 1: BelaSigna 200 Functional Block Diagram  
©2008 SCILLC. All rights reserved.  
June 2008 – Rev. 16  
Publication Order Number:  
BELASIGNA200/D  
 

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