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DP83848I PDF预览

DP83848I

更新时间: 2024-01-26 20:11:04
品牌 Logo 应用领域
美国国家半导体 - NSC 网络接口电信集成电路电信电路以太网局域网(LAN)标准以太网:16GBASE-T
页数 文件大小 规格书
82页 2700K
描述
Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

DP83848I 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QFP, QFP48,.35SQ,20Reach Compliance Code:not_compliant
风险等级:5.44数据速率:100000 Mbps
JESD-30 代码:S-PQFP-G48端子数量:48
收发器数量:1最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP48,.35SQ,20
封装形状:SQUARE封装形式:FLATPACK
电源:3.3 V认证状态:Not Qualified
子类别:Network Interfaces标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:ETHERNET TRANSCEIVER温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUADBase Number Matches:1

DP83848I 数据手册

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September 2005  
DP83848I PHYTER® - Industrial Temperature  
Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver  
General Description  
Features  
The DP83848I is a robust fully featured 10/100 single  
port Physical Layer device offering low power con-  
sumption, including several intelligent power down  
states. These low power modes increase overall prod-  
uct reliability due to decreased power dissipation. Sup-  
porting multiple intelligent power modes allows the  
application to use the absolute minimum amount of  
power needed for operation. In addition to low power,  
the DP83848I is optimized for cable length perfor-  
mance far exceeding IEEE specifications.  
Low-power 3.3V, 0.18µm CMOS technology  
Low power consumption < 270mW Typical  
3.3V MAC Interface  
Auto-MDIX for 10/100 Mb/s  
Energy Detection Mode  
25 MHz clock out  
SNI Interface (configurable)  
RMII Rev. 1.2 Interface (configurable)  
MII Serial Management Interface (MDC and MDIO)  
IEEE 802.3u MII  
IEEE 802.3u Auto-Negotiation and Parallel Detection  
IEEE 802.3u ENDEC, 10BASE-T transceivers and filters  
IEEE 802.3u PCS, 100BASE-TX transceivers and filters  
IEEE 1149.1 JTAG  
The DP83848I includes a 25MHz clock out. This  
means that the application can be designed with a  
minimum of external parts, which in turn results in the  
lowest possible total cost of the solution.  
The DP83848I easily interfaces to twisted pair media  
via an external transformer and fully supports JTAG  
IEEE specification 1149.1 for ease of manufacturing.  
Additionally both MII and RMII are supported ensuring  
ease and flexibility of design.  
The DP83848I features integrated sublayers to sup-  
port both 10BASE-T and 100BASE-TX Ethernet proto-  
cols, which ensures compatibility and interoperability  
with all other standards based Ethernet solutions.  
Integrated ANSI X3.263 compliant TP-PMD physical sub-  
layer with adaptive equalization and Baseline Wander com-  
pensation  
Programmable LED support Link, 10 /100 Mb/s Mode, Activ-  
ity, and Collision Detect  
Single register access for complete PHY status  
10/100 Mb/s packet BIST (Built in Self Test)  
48-pin LQFP package (7mm) x (7mm)  
The DP83848I is offered in a small form factor (48 pin  
LQFP) so that a minimum of board space is needed.  
Applications  
High End Peripheral Devices  
Industrial Controls and Factory Automation  
General Embedded Applications  
System Diagram  
10BASE-T  
or  
100BASE-TX  
DP83848I  
MPU/CPU  
MII/RMII/SNI  
10/100 Mb/s  
25 MHz  
Status  
LEDs  
Clock  
Source  
Typical Application  
®
PHYTER is a registered trademark of National Semiconductor.  
© 2005 National Semiconductor Corporation  
www.national.com  
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