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54LS174FMQB PDF预览

54LS174FMQB

更新时间: 2024-02-15 11:58:40
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器锁存器逻辑集成电路
页数 文件大小 规格书
8页 177K
描述
Hex/Quad D Flip-Flops with Clear

54LS174FMQB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:CERAMIC, LCC-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.25
Is Samacsys:N系列:LS
JESD-30 代码:S-CQCC-N20JESD-609代码:e0
长度:8.89 mm逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:25000000 Hz最大I(ol):0.004 A
位数:6功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):26 mA
传播延迟(tpd):36 ns认证状态:Not Qualified
筛选级别:MIL-STD-883 Class B座面最大高度:1.905 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:8.89 mm
最小 fmax:30 MHzBase Number Matches:1

54LS174FMQB 数据手册

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June 1989  
54LS174/DM54LS174/DM74LS174,  
54LS175/DM54LS175/DM74LS175  
Hex/Quad D Flip-Flops with Clear  
General Description  
Features  
Y
Y
Y
Y
Y
LS174 contains six flip-flops with single-rail outputs  
These positive-edge-triggered flip-flops utilize TTL circuitry  
to implement D-type flip-flop logic. All have a direct clear  
input, and the quad (175) versions feature complementary  
outputs from each flip-flop.  
LS175 contains four flip-flops with double-rail outputs  
Buffered clock and direct clear inputs  
Individual data input to each flip-flop  
Applications include:  
Buffer/storage registers  
Shift registers  
Pattern generators  
Information at the D inputs meeting the setup time require-  
ments is transferred to the Q outputs on the positive-going  
edge of the clock pulse. Clock triggering occurs at a particu-  
lar voltage level and is not directly related to the transition  
time of the positive-going pulse. When the clock input is at  
either the high or low level, the D input signal has no effect  
at the output.  
Y
Y
Y
Typical clock frequency 40 MHz  
Typical power dissipation per flip-flop 14 mW  
Alternate  
Military/Aerospace  
device  
(54LS174,  
54LS175) is available. Contact a National Semiconduc-  
tor Sales Office/Distributor for specifications.  
Connection Diagrams  
Dual-In-Line Package  
Dual-In-Line Package  
TL/F/6404–1  
Order Number 54LS174DMQB, 54LS174FMQB,  
54LS174LMQB, DM54LS174J,  
TL/F/6404–2  
Order Number 54LS175DMQB, 54LS175FMQB,  
54LS175LMQB, DM54LS175J  
DM54LS174W, DM74LS174M or DM74LS174N  
See NS Package Number E20A, J16A,  
M16A, N16E or W16A  
DM54LS175W, DM74LS175M or DM74LS175N  
See NS Package Number E20A, J16A,  
M16A, N16E or W16A  
Function Table (Each Flip-Flop)  
e
H
L
High Level (steady state)  
Low Level (steady state)  
Don’t Care  
Inputs  
Clock  
Outputs  
e
e
²
Q
Clear  
D
Q
X
e
Transition from low to high level  
u
0
L
H
H
H
X
u
u
L
X
H
L
L
H
L
H
e
Q
The level of Q before the indicated steady-state input conditions were  
established.  
L
H
e
²
LS175 only  
X
Q
Q
0
0
C
1995 National Semiconductor Corporation  
TL/F/6404  
RRD-B30M105/Printed in U. S. A.  

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