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54F377DM PDF预览

54F377DM

更新时间: 2024-01-13 20:48:22
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器锁存器逻辑集成电路时钟
页数 文件大小 规格书
8页 145K
描述
Octal D Flip-Flop with Clock Enable

54F377DM 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:SLIM, CERAMIC, DIP-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.3其他特性:WITH HOLD MODE
系列:F/FASTJESD-30 代码:R-CDIP-T20
逻辑集成电路类型:D FLIP-FLOP位数:8
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):12 ns
认证状态:Not Qualified最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子形式:THROUGH-HOLE
端子位置:DUAL触发器类型:POSITIVE EDGE
最小 fmax:100 MHzBase Number Matches:1

54F377DM 数据手册

 浏览型号54F377DM的Datasheet PDF文件第2页浏览型号54F377DM的Datasheet PDF文件第3页浏览型号54F377DM的Datasheet PDF文件第4页浏览型号54F377DM的Datasheet PDF文件第5页浏览型号54F377DM的Datasheet PDF文件第6页浏览型号54F377DM的Datasheet PDF文件第7页 
May 1995  
54F/74F377  
Octal D Flip-Flop with Clock Enable  
General Description  
Features  
Y
Ideal for addressable register applications  
The ’F377 has eight edge-triggered, D-type flip-flops with  
individual D inputs and Q outputs. The common buffered  
Clock (CP) input loads all flip-flops simultaneously, when the  
Clock Enable (CE) is LOW.  
Y
Clock enable for address and data synchronization  
applications  
Y
Y
Y
Y
Y
Y
Eight edge-triggered D flip-flops  
Buffered common clock  
The register is fully edge-triggered. The state of each D in-  
put, one setup time before the LOW-to-HIGH clock tran-  
sition, is transferred to the corresponding flip-flop’s Q out-  
put. The CE input must be stable only one setup time prior  
to the LOW-to-HIGH clock transition for predictable opera-  
tion.  
See ’F273 for master reset version  
See ’F373 for transparent latch version  
See ’F374 for TRI-STATE version  
É
Guaranteed 4000V minimum ESD protection  
Package  
Commercial  
74F377PC  
Military  
Package Description  
Number  
N20A  
J20A  
20-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F377DM (QB)  
20-Lead Ceramic Dual-In-Line  
74F377SC (Note 1)  
74F377SJ (Note 1)  
M20B  
M20D  
W20A  
E20A  
20-Lead (0.300 Wide) Molded Small Outline, JEDEC  
×
20-Lead (0.300 Wide) Molded Small Outline, EIAJ  
×
54F377FM (QB)  
54F377LM (QB)  
20-Lead Cerpack  
20-Lead Ceramic Leadless Chip Carrier, Type C  
e
Note 1: Devices also available in 13 reel. Use suffix  
×
SCX and SJX.  
Logic Symbols  
IEEE/IEC  
TL/F/9525–1  
TL/F/9525–4  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9525  
RRD-B30M75/Printed in U. S. A.  

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