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54F273DM PDF预览

54F273DM

更新时间: 2024-02-23 03:40:18
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器锁存器逻辑集成电路
页数 文件大小 规格书
8页 169K
描述
Octal D Flip-Flop

54F273DM 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.31系列:F/FAST
JESD-30 代码:R-CDIP-T20逻辑集成电路类型:D FLIP-FLOP
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):11 ns认证状态:Not Qualified
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:MILITARY
端子形式:THROUGH-HOLE端子位置:DUAL
触发器类型:POSITIVE EDGE最小 fmax:100 MHz
Base Number Matches:1

54F273DM 数据手册

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May 1995  
54F/74F273  
Octal D Flip-Flop  
General Description  
Features  
Y
Ideal buffer for MOS microprocessor or memory  
Eight edge-triggered D flip-flops  
The ’F273 has eight edge-triggered D-type flip-flops with in-  
dividual D inputs and Q outputs. The common buffered  
Clock (CP) and Master Reset (MR) inputs load and reset  
(clear) all flip-flops simultaneously.  
Y
Y
Y
Y
Y
Y
Y
Buffered common clock  
Buffered, asynchronous Master Reset  
See ’F377 for clock enable version  
See ’F373 for transparent latch version  
The register is fully edge-triggered. The state of each D in-  
put, one setup time before the LOW-to-HIGH clock tran-  
sition, is transferred to the corresponding flip-flop’s Q out-  
put.  
See ’F374 for TRI-STATE version  
É
Guaranteed 4000V minimum ESD protection  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The  
device is useful for applications where the true output only is  
required and the Clock and Master Reset are common to all  
storage elements.  
Package  
Commercial  
74F273PC  
Military  
Package Description  
Number  
N20A  
J20A  
20-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F273DM (Note 2)  
20-Lead Ceramic Dual-In-Line  
74F273SC (Note 1)  
74F273SJ (Note 1)  
M20B  
M20D  
W20A  
E20A  
20-Lead (0.300 Wide) Molded Small Outline, JEDEC  
×
20-Lead (0.300 Wide) Molded Small Outline, EIAJ  
×
54F273FM (Note 2)  
54F273LM (Note 2)  
20-Lead Cerpack  
20-Lead Ceramic Leadless Chip Carrier, Type C  
e
Note 1: Devices also available in 13 reel. Use suffix  
SCX and SJX.  
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix  
e
DMQB, FMQB and LMQB.  
Logic Symbols  
IEEE/IEC  
TL/F/9511–3  
TL/F/9511–5  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9511  
RRD-B30M75/Printed in U. S. A.  

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