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54F175LM PDF预览

54F175LM

更新时间: 2024-01-25 05:12:19
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器逻辑集成电路
页数 文件大小 规格书
8页 170K
描述
Quad D Flip-Flop

54F175LM 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliant风险等级:5.73
Is Samacsys:NBase Number Matches:1

54F175LM 数据手册

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November 1994  
54F/74F175 Quad D Flip-Flop  
General Description  
Features  
Y
Edge-triggered D-type inputs  
The ’F175 is a high-speed quad D flip-flop. The device is  
useful for general flip-flop requirements where clock and  
clear inputs are common. The information on the D inputs is  
stored during the LOW-to-HIGH clock transition. Both true  
and complemented outputs of each flip-flop are provided. A  
Master Reset input resets all flip-flops, independent of the  
Clock or D inputs, LOW.  
Y
Buffered positive edge-triggered clock  
Y
Asynchronous common reset  
Y
True and complement output  
Y
Guaranteed 4000V minimum ESD protection  
Package  
Commercial  
74F175PC  
Military  
Package Description  
Number  
N16E  
J16A  
16-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F175DM (Note 2)  
16-Lead Ceramic Dual-In-Line  
74F175SC (Note 1)  
74F175SJ (Note 1)  
M16A  
M16D  
W16A  
E20A  
16-Lead (0.150 Wide) Molded Small Outline, JEDEC  
×
16-Lead (0.300 Wide) Molded Small Outline, EIAJ  
×
54F175FM (Note 2)  
54F175LM (Note 2)  
16-Lead Cerpack  
20-Lead Ceramic Leadless Chip Carrier, Type C  
e
Note 1: Devices also available in 13 reel. Use suffix  
SCX and SJX.  
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix  
e
DMQB, FMQB and LMQB.  
Logic Symbols  
Connection Diagrams  
Pin Assignment for  
DIP, SOIC and Flatpak  
Pin Assignment  
for LCC  
IEEE/IEC  
TL/F/9490–1  
TL/F/9490–2  
TL/F/9490–5  
TL/F/9490–3  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9490  
RRD-B30M75/Printed in U. S. A.  

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